Multiple precursor cyclical deposition system

a cyclical deposition and precursor technology, applied in chemical vapor deposition coating, coating, metallic material coating process, etc., can solve the problems of large amount of ongoing effort, many traditional deposition processes have difficulty filling sub-micron structures,

Inactive Publication Date: 2005-01-25
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities.
Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 4:1.
Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free and seam-free sub-micron features having high aspect ratios.

Method used

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  • Multiple precursor cyclical deposition system
  • Multiple precursor cyclical deposition system
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Examples

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Embodiment Construction

Process Chamber Adapted for Cyclical Deposition

FIGS. 1, 1A, and 2 are drawings of exemplary embodiments of a processing system that may be used to perform cyclical deposition. The term “cyclical deposition” as used herein refers to the sequential introduction of reactants to deposit a thin layer over a structure and includes processing techniques such as atomic layer deposition and rapid sequential chemical vapor deposition. The sequential introduction of reactants may be repeated to deposit a plurality of thin layers to form a layer to a desired thickness. Not wishing to be bound by theory, it is believed that the mode of deposition of cyclical deposition provides conformal coverage over substrate structures.

FIG. 1 is a partial cross-sectional perspective view of one embodiment of a processing system 100. The processing system 100 comprises a lid assembly 120 includes a lid plate 122, a manifold block 150, one or more valves (one valve 155A is shown in FIG. 1), one or more reservoi...

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Abstract

Embodiments of the present invention relate to an apparatus and method of cyclical deposition utilizing three or more precursors in which delivery of at least two of the precursors to a substrate structure at least partially overlap. One embodiment of depositing a ternary material layer over a substrate structure comprises providing at least one cycle of gases to deposit a ternary material layer. One cycle comprises introducing a pulse of a first precursor, introducing a pulse of a second precursor, and introducing a pulse of a third precursor in which the pulse of the second precursor and the pulse of the third precursor at least partially overlap. In one aspect, the ternary material layer includes, but is not limited to, tungsten boron silicon (WBxSiy), titanium silicon nitride (TiSixNy), tantalum silicon nitride (TaSixNy), silicon oxynitride (SiOxNy), and hafnium silicon oxide (HfSixOy). In one aspect, the composition of the ternary material layer may be tuned by changing the flow ratio of the second precursor to the third precursor between cycles.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionEmbodiments of the present invention generally relate to an apparatus and method of deposition utilizing multiple precursors. More particularly, embodiments of the present invention relate to an apparatus and method of cyclical deposition utilizing multiple precursors in which delivery of at least two of the precursors to a substrate structure at least partially overlap.2. Description of the Related ArtReliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): C23C16/455C23C16/44
CPCC23C16/45531C23C16/45561C23C16/45544
Inventor YANG, MICHAEL XIYOON, HYUNGSUK ALEXANDERZHANG, HUIFANG, HONGBINXI, MING
Owner APPLIED MATERIALS INC
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