Power management circuit and memory cell

Abstract

A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at a predetermined level, such that the memory cell operates in standby mode. A latch circuit is coupled between the power voltage, the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal when the memory cell operates in the standby mode.

Description

BACKGROUND OF THE INVENTION[0001]1. Technical Field[0002]The present disclosure relates in general to a circuit for power management of a standard cell application. In particular, the present disclosure relates to a circuit for power management of a static random access memory (SRAM).[0003]2. Description of the Related Art[0004]Many integrated circuit devices, such as microprocessors, include on-board memory devices, such as SRAM devices. For example, SRAM devices are commonly used as cache memory because of their relatively fast speed. SRAM devices are also sold as stand-alone integrated circuits for use as cache memory and for other uses. SRAM devices are also more suitable for use as cache memory than dynamic random access memory (“DRAM”) devices because they need not be refreshed, thus making all SRAM memory cells continuously available for a memory access.[0005]FIG. 1 is a block diagram of a portion of a typical array 10 of SRAM cells 12 arranged in rows and columns. A pluralit...

AI Technical Summary

Benefits of technology

The present invention provides a circuit for power management of memory cells using switches and latches to preserve the output state of the memory cells. The circuit includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, and a latch circuit. The first PMOS transistor has a first gate, a first drain, and a first source coupled to the power voltage. The first NMOS transistor has a second gate, a second drain, and a second source coupled to the ground voltage. The first switch is connected between the first bit line and the first terminal, and the second switch is connected between the second bit line and the second terminal. The latch circuit is connected between the power voltage, the first terminal, and the second terminal to preserve the voltage levels of the first terminal and the second terminal. The circuit allows for standby mode where the power voltage is disconnected from the memory cell and the latch circuit is used to preserve the voltage levels. The technical effect of the invention is to improve the power management of memory cells and reduce power consumption.

Problems solved by technology

However, the conventional circuits described suffer standby leakage problems when the circuits are in standby mode.

Standby leakage problems are serious concerns in very deep submicron technology with device size reductions, causing output state of memory cells changed. FIG. 3 shows current leakage sources in a transistor 40.

The increased subthreshold leakage and gate leakage current not only increase the IC reliability issues, but also increase the package cost in order to handle the excess power dissipation.

The rapidly increased leakage current leads the huge power consumption when the IC chip is getting larger, faster and denser.

Thus, power management techniques become a required design issue.

Some design issues and limitations, however, were not addressed by the patent.

The NMOS transistor leakage issue, however, still exist.

In addition, the back-biased MOS method presents junction breakdown and gate oxide breakdown concerns and offers limited power savings in very deep submicron technology.

Very deep submicron technology has less efficient threshold voltage variation due to use of the backed-gate bias, thus it cannot solve the gate leakage problem for 90 nm technology and beyond.

However, powering down all the memory cells results in the loses of the data stored therein, and a power regular is required to reduce the power supply voltage, thus increasing the design difficulty.

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