Web-enabled solutions for memory compilation to support pre-sales estimation of memory size, performance and power data for memory components

Abstract

A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.

Description

TECHNICAL FIELD[0001]Embodiments generally relate to data-processing methods and systems. Embodiments also relate to data-processing networks. Embodiments also relate to improving manufacturing flow for the manufacturing of memory components in a manufacturing environment.BACKGROUND[0002]ASIC designs are becoming more memory dependant. It is a common design practice in all market segments to embed as much memory as possible to increase the performance of the design. Even though memory content per design increases between technology nodes, maximum compilable memory macro per instance is decreasing. With these diverging factors, large memory instances are implemented through numerous smaller instances. This implementation method can create a number of issues during front-end and back-end design phases. During the front-end design phase, for example resources are required to select the correct smaller configuration to assemble the original large memory configuration. Such a phase can r...

AI Technical Summary

Benefits of technology

This solution significantly reduces turn-around-time by automating memory selection and generation, allowing for efficient management of large memory configurations, and enables faster data extraction and analysis, thereby improving resource utilization and design efficiency.

Problems solved by technology

This implementation method can create a number of issues during front-end and back-end design phases.

Such a phase can result in an iterative process because this technique does not take into account design priorities such as performance, density, and power considerations.

In addition, the higher the number of small instances utilized, the higher the routing complexity, and routing overhead that result.

A number of problems are associated with existing approaches.

For example, the lack of a user friendly automation process for assisting a designer in selecting memory instance implementation for a design based on functional memory requirements is one problem.

For large memory macros, for example this task becomes even more challenging, as FAEs must now determine the partition method for combining multiple instances to meet the original configuration and performance requirements.

The process is tedious, time consuming, and not the efficient way to utilize FAE resources.

In this case, the process is even more problematic because the customers do not have the familiarity with LSI memory compilers and tools that our FAEs do.

Other problems associated with existing solutions is the lack of a capability to input, generate, store and manage a large number of memory configurations / instances in a database and reduce TAT by automating and improving process of memory selection.

There is no tool to assist the designer in deciding whether particular memory configurations should be generated using SRAM or LBRAM.

In addition to such problems, the overall memory selection decisions at the pre-sales stage based on design priorities: density, performance, power cannot be easily made due to the many memory compiler options.

Additionally, present solutions do not provide a robust capability for “what if” and tradeoff analysis, suggestion of memory tiles for large Megabit memories.

No mechanism for store memory instances in a reusable manner is presently available in the context of such existing solutions.

Current solutions are limited in scope and applicability.

Such a process is highly inefficient and takes a great deal of time (e.g., days), thus impacting the turn around time to get a quote back to the customer.

Determining valid compiler options to be specified to Isimemory is time consuming.

The flow for generating power parameters is very complex and time consuming for FAE's to run on a daily basis.

Additionally, Virage tools are not available at every design center site.

Because Virage tools are not yet available for general release, there also exists very little in the way of training and documentations for FAE's other than what is provided by the software supplier.

Extracting data from such output files requires that certain pieces of data are estimated, rather than generated by running tools resulting in grossly inaccurate data or overestimated values.

In effect, such existing solutions result in an inefficient use of the FAE, the design center and customer resources during the manufacturing process.

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