Pocket counterdoping for gate-edge diode leakage reduction

Abstract

A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of Provisional Application Ser. No. 61 / 672,510 entitled “SELF-ALIGNED GATE-EDGE DIODE LEAKAGE REDUCTION IMPLANT”, filed Jul. 7, 2012, which is herein incorporated by reference in its entirety.FIELD[0002]Disclosed embodiments relate to semiconductor fabrication, more particularly to pocket (or halo) implantation and pocket regions for gate edge diode leakage reduction of Metal-Oxide Semiconductor (MOS) transistors.BACKGROUND[0003]For high-performance complementary MOS (CMOS) transistors, channel profile and source / drain extension (lightly doped drain (LDD)) engineering may be used. Lowering band-to-band (B2B) gate edge diode leakage (GDL) which results in off-state current leakage is a challenge particularly for low leakage (e.g., ultra-low-leakage (ULL)) high voltage threshold (HVT) MOS transistors. Self-aligned pockets (or halos) using the gate stack for self-alignment implanted around the LDDs can imp...

AI Technical Summary

Benefits of technology

This patent describes a method of making MOS transistors with reduced gate edge diode leakage (GDL) without affecting the threshold voltage or subthreshold leakage of the transistor. This is achieved through the use of two or more self-aligned pocket implants using the same mask pattern. The first implant provides initial doping, while the second implant provides additional counter-doping to create regions of lower net doping and lower electric field. These regions of lower doping and lower field are close enough to the source and drain extension and junctions to reduce GDL but do not intrude into the channel region of the transistor. This method is referred to as self-aligned GDL reduction pocket implants or simply GDL reduction pocket implants.

Problems solved by technology

Lowering band-to-band (B2B) gate edge diode leakage (GDL) which results in off-state current leakage is a challenge particularly for low leakage (e.g., ultra-low-leakage (ULL)) high voltage threshold (HVT) MOS transistors.

However, the typical pocket implant angle is limited to about 20 to 30 degrees because of blocking by protruding masking photoresist and / or the adjacent gate electrode (e.g., a polysilicon gate).

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