Non-volatile memory system having internal data verification test mode

Abstract

A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

Description

TECHNICAL FIELDThe present invention relates to non-volatile memory systems, and more specifically, to a memory system having a test mode of operation in which the data contained in the memory cells can be verified using the internal data verification process which is part of a programming or erase operation. This provides a test engineer with more reliable status information regarding the data contained in the memory cells then that obtained by performing a read operation or using external verification methods.BACKGROUND OF THE INVENTIONIn early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. This was referred to as external control of the memory system operations because the control means was external to the memory itself. Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations f...

AI Technical Summary

Benefits of technology

The present invention is directed to a memory system which includes means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. In one embodiment, the memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the test mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. The verification operation described provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

Problems solved by technology

Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations for optimizing their particular memories, many such systems now include an internal state machine (ISM) for controlling the operation of the memory system.

Thus, the sense amplifier operates with a substantial noise margin during a normal read operation because there is a significant voltage range between V.sub.ref and the programmed or erased threshold voltage of a cell.

However, it provides little information regarding small, but potentially important changes in the threshold voltage of the cell caused by electrons leaking from the floating gate of the cell.

Although this has the benefit of setting the reference voltage level at values which provide a more accurate assessment of the state of the memory cell, the method does have a disadvantage.

This is because noise in the circuit is generally insufficient in magnitude to produce a false positive in the output of the sense amplifier.

Since the two inputs of the sense amplifier are much closer to each other in this case than for a regular read operation, the sense amplifier's output is more susceptible to error due to noise and the sense amplifier responds much more slowly.

In this case, the two inputs of the sense amplifier are also much closer than in a regular read operation and the sense amplifier's output is again more susceptible to noise.

With noise of sufficient magnitude to produce a false positive, noise fluctuations will cause the sense amplifier output to be unstable.

The noise fed back to the sense amplifier can alter the output of the sense amplifier due to the small noise margin of the data input / output circuit when used with data verification reference voltage levels.

Thus, while this test mode of data verification is superior to a normal read operation, it is still susceptible to error owing to the noise produced by the output buffer.

Another disadvantage of this externally controlled data verification procedure is that it requires the test engineer to specify the address(es) of the memory cells to be verified.

This increases the time required to verify the contents of a large number of memory cells.

Yet another disadvantage of an externally controlled verification procedure which uses the regular read operation sensing path is that it requires the test engineer to specify the delay between the time the read operation is initiated and when the data indicating the state of the cell is read out.

This user specified delay is unlikely to match the delay the internal state machine uses during its internally controlled verification process.

The difference between the two time delays can lead to inconsistent results between the two procedures, and hence cause difficulties in correlating the results of the two verification processes.

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