Multiple network protocol encoder/decoder and data processor

Abstract

A multiple network protocol encoder / decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.

Description

BACKGROUND OF THE INVENTION[0001]1. Technical Field[0002]The invention relates to network protocols and data packets. More particularly, the invention relates to the decoding of network protocols and processing of packet data during packet reception without the time-consuming overhead of software or software / hardware implementations. In addition, the invention allows one pass parsing of the data, eliminating the buffering of data packets for different stacks, and thus minimizing the memory usage.[0003]2. Description of the Prior Art[0004]Computer networks necessitate the provision of various communication protocols to transmit and receive data. Typically, a computer network comprises a system of devices such as computers, printers and other computer peripherals, communicatively connected together. Data are transferred between each of these devices through data packets which are communicated through the network using a communication protocol standard. Many different protocol standard...

AI Technical Summary

Benefits of technology

[0008]The invention provides a low-cost, low-power, easily manufacturable, small form-factor network access module which has a low memory demand and provides a highly efficient protocol decode. The invention comprises a hardware-integrated system that both decodes multiple network protocols in a byte-streaming manner concurrently and processes packet data in one pass, thereby reducing system memory and form factor requirements, while also eliminating software CPU overhead.

[0010]The preferred embodiment does not necessarily require a CPU and software to process the network packets, thereby greatly reducing system cost. The hardware gate level implementation provides a modular, embeddable design whereupon the designer may pick and choose the functionality that the particular application requires and still retain a low cost, low power, small form factor.

Problems solved by technology

The result of this implementation, however, is that the system requires a high processor overhead, a large amount of system memory, complicated configuration setup on the part of the computer user to coordinate the different software protocol and data handlers communicating to the computer's Operating System (O.S.) and computer and network hardware.

It is evident that the amount of processing overhead required to process a protocol is very high and extremely cumbersome and lends itself to applications with a powerful Central Processing Unit (CPU) and a large amount of memory.

Most of these products have small footprints, 8-bit controllers, limited memory or require a very limited form factor.

The previously mentioned protocol implementations require too much hardware and processor power to meet these requirements.

The complexity of such implementations are difficult to incorporate into consumer products in a cost effective way.

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