Dynamic memory and its manufacturing method

Abstract

Dynamic memory cell, a conductive surface-tape contact (20) is the conductive connection between a channel-capacitor (1) and a proliferation district (3) of an planar selecting transistor (2) formed by the channel-capacitor (1) and a DRAM memory cell (101) of the planar selecting transistor (2), and the contact (20) is located above the substrate surface and at least covers part of the proliferation district (3). Memory nodes (15) of the channel Capacitor (1) is closed by at least one oxide ring sheath (21), which can insulate the memory nodes (15) and the proliferation district (3, 4) at the substrate side. An oxide cover(23) is provided on the oxide ring sheath (21). An opening (24) filled up with a conductive material, located in the oxide cover(23), is connected to the conductive surface-tape contact, and the scope of the opening ( 24) is extended vertically from the surface of the oxide cover(23) to the memory node (15). A favorable configuration has a memory cellular field formed by a plurality of MINT memory cells with a area of 8 F # + [2], wherein the initiative area is formed by a plurality of strip memory cells on the beam.

Description

technical field [0001] The invention relates to an integrated dynamic memory unit with a planar selection transistor and a trench capacitor. Background technique [0002] The dynamic memory is generally formed by a single-transistor cell field, and each single-transistor cell constituting the single-transistor cell field usually has a selection transistor and a trench capacitor. Random access to the data stored in the storage node of the trench capacitor is performed through a word line forming the gate contact of a select transistor with a substrate. Data is read via a bit line connected to the first doped diffusion. Applying an electric pulse to the word line can turn on the first doped diffusion region and the second doped diffusion region (that is, the second doped diffusion region connected to the storage node of the trench capacitor) in the cell. Conductive connection between. Possible charging states of the trench capacitor are logic state "0" and / or logic state "1...

AI Technical Summary

Problems solved by technology

[0011] Therefore task of the present invention is to propose a kind of DRAM (Dynamic Random Access Memory) storage unit structure, this DRAM storage unit structure will be able to realize that storage unit area is 8F on the one hand 2 On the other hand, it must be able to solve the problem of out-diffusion caused by the distance between the channel and / or the channel capacitor and the gate contact can no longer be reduced.

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