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Improvement for ESD transistor source leaked capacitance

A technology of transistors and source-drain junctions, applied in circuits, electrical components, electric solid-state devices, etc., can solve the problem of excessive source-drain junction capacitance and device speed, and achieve the effect of increasing junction capacitance and reducing breakdown voltage

Active Publication Date: 2007-12-05
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a method for improving the capacitance of the source-drain junction of the ESD transistor, which can effectively solve the problem of too low device speed due to the excessive source-drain junction capacitance of the ESD device in the conventional process

Method used

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  • Improvement for ESD transistor source leaked capacitance
  • Improvement for ESD transistor source leaked capacitance

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Embodiment Construction

[0012] As shown in Figures 1 and 2 (the gray area in the figure is the ESD ion implantation area), the main difference between the present invention and the traditional process is that the area of ​​the ESD ion implantation area is reduced, which reduces the damage caused by the ESD while ensuring the normal operation of the ESD device. The increase in the source-drain junction capacitance caused by the injection.

[0013] When the method of the present invention is specifically implemented, it is first necessary to make an ESD lithography plate, which only opens the drain part of a small number of ESD transistors that need to be implanted with ESD ions. The specific implementation steps are: after the source and drain ion implantation of the conventional process NMOS device is completed, insert the ESD lithography plate, and perform ESD ion implantation, after removing the photoresist, return to the conventional process flow.

[0014] Since the present invention only performs ESD...

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Abstract

The invention adopts a dedicated photo mask for use in ESD ion implantation. The photo mask only opens a regional area on the drain end to be implanted into ion, and the ESD ion implantation is made for the said regional area on the drain electrode.

Description

Technical field [0001] The present invention relates to a manufacturing process method of a semiconductor device, in particular to a method for reducing the source and drain junction capacitance of an electrostatic protection tube that plays a protective role in a semiconductor integrated circuit. Background technique [0002] ESD (electrostatic discharge) devices are electrostatic protection tubes that must be used in circuit design. Its working principle is that under transient high voltage, the drain terminal of ESD breaks down, and the resulting breakdown current makes the parasitic bipolar transistor composed of ESD source, substrate and drain turn on. Due to the amplification of the current of the parasitic tube, the ESD device is caused. The current-voltage characteristics of the sine have a negative resistance relationship, and then the leakage current increases rapidly with the increase of the leakage voltage, so that the transient current of the core circuit is shunted ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/336H01L21/265H01L23/60H01L29/92
Inventor 姚泽强钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP