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Method for fabricating strained-silicon CMOS transistors

A technology of oxide semiconductors and transistors, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as the inability to greatly improve the performance of CMOS transistors

Active Publication Date: 2008-08-13
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method can use the silicon germanium in the epitaxial layer to promote the movement of carriers in the substrate, due to the barrier of the spacer, the silicon germanium cannot be placed in the substrate very close to the channel region, and thus cannot greatly improve the performance of the CMOS transistor. efficacy

Method used

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  • Method for fabricating strained-silicon CMOS transistors
  • Method for fabricating strained-silicon CMOS transistors
  • Method for fabricating strained-silicon CMOS transistors

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Embodiment Construction

[0045] Please refer to Figure 5 to Figure 12 , Figure 5 to Figure 12 A schematic diagram of fabricating a strained silicon CMOS transistor for the present invention. Such as Figure 5 As shown, a semiconductor substrate 200 is firstly provided with a shallow trench isolation (shallow trench isolation, STI) 206 to separate the NMOS transistor region 202 and the PMOS transistor region 204, and each of the NMOS transistor region 202 and the PMOS transistor region 204 has a gate structure. Wherein, the NMOS gate structure includes an NMOS gate 208 and a gate dielectric layer 214 disposed between the NMOS gate 208 and the semiconductor substrate 200, and the PMOS gate structure includes a PMOS gate 210 and a gate dielectric layer 214 disposed between the PMOS gate 208 and the semiconductor substrate 200. A gate dielectric layer 214 between the gate 210 and the semiconductor substrate 200 . Next, an offset spacer 212 made of a silicon oxide layer or a silicon nitride layer is re...

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Abstract

A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source / drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.

Description

technical field [0001] The invention relates to a method for manufacturing a strained silicon complementary metal oxide semiconductor transistor. Background technique [0002] As the line width of the semiconductor process continues to shrink, the size of the MOS transistor is also continuously miniaturized. However, when the line width of the semiconductor process has developed to the bottleneck, how to increase the carrier mobility to increase the MOS transistor Speed ​​has become a major issue in the field of semiconductor technology today. In the currently known technology, there is a MOS transistor using strained silicon as a substrate, which utilizes the different characteristics of the lattice constant of silicon germanium (SiGe) and single crystal silicon (single crystal Si), so that silicon germanium (SiGe) The epitaxial layer is structurally strained to form strained silicon. Since the lattice constant of the silicon germanium layer is larger than that of silicon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 丁世汎黄正同吴劲昌李坤宪洪文瀚郑礼贤沈泽民郑子铭李年中
Owner UNITED MICROELECTRONICS CORP