Method for manufacturing carrying-plate for packaging flat plastic-sealed ball grid array and its carrying plate

Abstract

The invention supplies a carrier plate manufacture method used in flat plastic package ball shelf array packaging. The traditional carrier plate has the problem that it cannon do electrical property testing before packaging. The manufacture method includes the following steps that preparing a two sides coller clad plate; utilizing chemical milling technology to form base piece surface circuitry, bonding pad, and electroplating bus on the coller clad plate; the first protection film is formed between the base piece surface circuitry and the electroplating bus; exposing the bonding pad area demanded electroplating metal; then it is putted into the electroplating solution to electroplate, the electroplating coating is formed on the bonding pad; the first protection film is eliminated; the second is formed at the surface of the carrier plate; exposing the electroplating bus; the bus is eliminated by utilizing the chemical milling technology. The carrier plate made by this method can do electrical property testing before packaging, so that all of the carrier plates used to pack will be affirmed qualified.

Description

technical field [0001] The invention relates to an integrated circuit packaging process, in particular to a manufacturing method for a carrier plate used in flat plastic-encapsulated ball grid array packaging. Background technique [0002] Flat plastic ball grid array packaging is a semiconductor packaging method that has developed rapidly in recent years. This packaging method has the advantages of small size, light weight, high production efficiency, and low unit cost. It has a very wide range of applications in the semiconductor manufacturing industry. application. [0003] The following is a brief description of the structure and manufacturing process of the existing flat plastic ball grid array packaging technology: [0004] First, a carrier is prepared, the structure of which is shown in Figures 1A and 1B. The carrier includes a plurality of parallel substrates 100, and each substrate 100 is divided into a plurality of device units 101, and the device units 101 are pr...

AI Technical Summary

Problems solved by technology

But, since the pad 107 required by the gold wire bonding process on the substrate has the process needs of electroplating gold, so each wire connected to the pad 106 must extend to the outer edge of the single device unit 101, and be connected to the outer edge of the unit. The electroplating bus 104 is connected to each other, and this method makes it impossible to conduct an electrical test on the entire carrier board before the dicing is completed, that is, it is impossible to confirm whether the carrier board and the wire bonding are defective before the chip packaging is completed

Although today's quality management system is highly developed, most semiconductor processing enterprises can reduce the variation in the production process to a very small degree, but it is almost impossible to achieve 100% yield rate, which leads to the following For the above problem, if it is impossible to confirm whether there is a defect on the carrier board before packaging, it will cause a chip with no problem in function to be mounted on a defective carrier board. Such a situation occurs, which will lead to the appearance of defective products.

[0009] As we all know, in the production process of semiconductor devices, the cost of the chip is many times higher than the cost of the entire package, and the occurrence of such defects has caused unnecessary waste and led to a substantial increase in production costs

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