Request-based low-power consumption command memory

Abstract

This invention discloses one kind of a low-power instruction memory based on request l. Its pulse generator uses the memory clock generation logic based on request, separately generates the reading pulse clock and writing pulse clock according to the request of reading and writing, and generates read hold and write hold to control the reading address generator and the writing address generator. The reading address generator and the writing address generator are separately used for the generating the reading and the writing address. The instruction loading module is responsible for interacting with the system external wide frequency data, and splicing instructions, completing the splicing instructions to be transmitted to the half frequency memory. The instruction reading module is used for providing with half frequency memory and the entire frequency instruction assembly line as high speed instruction transmission. The instruction memory is used for storing instructions, each line saves two consecutive instruction packets, and each of the read / write catamaran instruction storages takes two packets as the unit. This invention has the merits: the low-power, the high basic frequency, the high throughput, and the simple control and so on.

Description

technical field [0001] The invention mainly relates to the field of memory design in a microprocessor, in particular to a request-based low-power consumption instruction memory. Background technique [0002] With the rapid increase of the scale of integrated circuits, power consumption has gradually become the bottleneck of integrated circuit design, so low power consumption design has become an important goal and basic requirement for microprocessor design. In today's mainstream microprocessors, in order to solve the huge speed gap between the processor and the main memory, on-chip storage technology is used, with a capacity of mega-level. For example, the capacity of Intel Itanium2 on-chip memory is 3.288 megabytes, including 16KB ICache, 16KB DCache, 256KB L2Cache and 3M L3Cache. The power consumption brought by such a large-capacity on-chip memory has become an important source of microprocessor power consumption, so reducing the power consumption of the on-chip memory ...

AI Technical Summary

Problems solved by technology

However, since the source of the gated clock still comes from the global clock, the storage access frequency in this mode is the same as that under the control of the global clock, and is limited by the access time of the SRAM.

Although SRAM has faster speed and shorter access time than other types of memory, generally at the nanosecond (ns) level, it still cannot meet the storage access delay requirements of high-frequency processor pipelines in terms of practical applications. The megahertz pipeline has a clock cycle of only 1 nanosecond, which is 1 to 2 times smaller than the access delay of SRAM

Although the gated clock on-chip memory design solves the problem of low power consumption in memory design, it cannot overcome the frequency limitation

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