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Improvig technique for reducing defect of metalic wire

A metal wire and defect technology, which is applied in the field of improved technology for reducing metal wire defects, can solve problems such as the effective prevention of Al voids, and achieve the effects of reducing Al voids, a simple process flow, and a reduced thickness

Inactive Publication Date: 2009-06-10
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, this approach is not as effective in preventing Al voids as people expect, especially in large-scale production processes (HDP-CVD) deposited SiO 2 The temperature sometimes exceeds 400°C (for example, at 400-450°C), and Ti and Al react to form TiAl 3 The temperature is ≥350℃

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0014] 1. Preparation of bottom layer Ti / TiN sputtering film: At present, Endura5500 equipment (Applied Materials, Inc., USA) is commonly used for sputtering in the production line. The Ti and TiN films are deposited sequentially in the Ti / TiN sputtering chamber with a conventional process, and the thicknesses are 10nm and 25nm respectively.

[0015] 2. Sputtering of the Al layer: In the Al sputtering chamber, the composition of the Al target is Al-Cu, Cu accounts for 1%, the sputtering film thickness is 420 nm; the sputtering temperature is 300°C.

[0016] 3. Preparation of Ti / TiN sputtered film on the top layer: Ti and TiN films were sequentially formed on the Al layer by the method of step 1, with thicknesses of 10nm and 25nm respectively.

[0017] 4. After etching the bottom-up metal wire structure of Ti, TiN, Al, Ti, TiN, it needs to be annealed in the furnace, temperature: 440℃, annealing gas: N 2 -H 2 (10%H 2 ). Then HDP-CVD deposited SiO 2 .

Embodiment 2

[0019] 1. The sputtering equipment is the same as in Example 1, and the underlying Ti / TiN films are formed sequentially from bottom to top, and the thicknesses are 5nm and 30nm respectively.

[0020] 2. Al layer deposition is carried out, the composition of the Al target is Al-Cu, Cu accounts for 0.8%, the sputtering film thickness is 400 nm; the sputtering temperature is 250°C.

[0021] 3. Deposit Ti / TiN sequentially on the Al layer by the method of step 1, and the film thicknesses are 5nm and 30nm respectively.

[0022] 4. Etching and annealing the metal wire structure formed above respectively Ti, TiN, Al, Ti, TiN from bottom to top, the temperature is 460°C, and the annealing gas is N 2 -H 2 , H 2 5%. Then HDP-CVD deposited SiO 2 .

Embodiment 3

[0024] 1. The sputtering equipment is the same as in Example 1, and the underlying Ti / TiN films are formed sequentially from bottom to top, and the thicknesses are 15nm and 20nm respectively.

[0025] 2. Al layer deposition is carried out, the composition of the Al target is Al-Cu, Cu accounts for 1.2%, the sputtering film thickness is 440 nm; the sputtering temperature is 350°C.

[0026] 3. Deposit Ti / TiN sequentially on the Al layer by the method of step 1, with film thicknesses of 15nm and 20nm respectively.

[0027] 4. Etching and annealing the above formed metal wire structure respectively Ti, TiN, Al, Ti, TiN from bottom to top, the temperature is 420°C, and the annealing gas is N 2 -H2,H 2 15%. Then HDP-CVD deposited SiO 2 .

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Abstract

Technique in the invention includes following points: (1) reducing Ti / TiN thickness above and below Al layer; (2) reducing thickness of Al layer, and reducing sputtering temperature; (3) increasing Cu content in Al target; (4) increasing annealing temperature for etched metal wire. The invention restrains occurring of great amount of Al caverne, possessing features of simple technique, easy of operation, high yield and raising reliability of interconnection and rate of finished products.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to an improved technology for reducing metal line defects. Background technique [0002] Al wire interconnection is indispensable in the semiconductor chip manufacturing process, especially in the semiconductor manufacturing process with a feature size larger than 0.35 μm. Usually, the structure of the Al line layer is a sandwich structure, that is, the bottom layer is Ti / TiN, the middle layer is Al-Cu (0.5-1% Cu), and the upper layer is Ti / TiN. Sputtering is divided into two times: the first sputtering bottom layer is Ti / TiN, and the second sputtering is Al / Ti / TiN. [0003] As the size of devices shrinks, the size of metal lines shrinks at the same time. Especially in the semiconductor manufacturing process of 0.25 μm and below, Al appears in the metal lines of Ti / TiN / Al / Ti / TiN (usually with a thickness of 30 / 110 / 470 / 2...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3205H01L21/321
Inventor 缪炳有
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT