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Dynamic RAM device with data-handling capacity

A data processing and dynamic random technology, applied in the field of memory, can solve the problems that memory chips cannot meet the timing protocol and cannot be effectively integrated, and achieve the effects of low power consumption, improved performance, and high performance

Inactive Publication Date: 2010-01-13
戴葵
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these memory chips cannot be effectively integrated into existing data processing systems because they cannot meet the timing protocol of existing memories

Method used

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  • Dynamic RAM device with data-handling capacity
  • Dynamic RAM device with data-handling capacity
  • Dynamic RAM device with data-handling capacity

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Embodiment Construction

[0026] The realization of the object of the present invention, function characteristic will be described further with reference to accompanying drawing in conjunction with embodiment.

[0027] The DRAM memory device with data processing capability is divided into functional modules, including a memory interface, a processing unit, a processing unit control interface, a communication network, an internal DRAM memory, and an internal DRAM storage controller. The memory interface is used to exchange data with the external memory bus, and at the same time, it is connected to the DRAM controller in the device and the control interface of the processing unit. The processing unit is connected to the DRAM controller in the device through a communication network, and the DRAM controller is also connected to the internal DRAM memory. In the best embodiment, we adopt the standard DDR2 interface and specification, and integrate 4 eDRAM on-chip memories of each 64KByte size and 4 processing...

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Abstract

The invention relates to a DRAM storage device provided with data processing ability, comprising a storage interface, a processing unit, a control interface of the processing unit, an internal storage, a communication network and an internal DRAM storage controller, wherein the storage interface is used to interact data with an external storage bus, and is connected with the internal DRAM controller in the device and the control interface of the processing unit, the processing unit and the internal DRAM controller are connected with each other by the communication network, and the DRAM controller is also connected with the internal DRAM storage. The invention can apply the device to a variety of data processing systems under the condition of unchanging any hardware, and the invention not only can provide storage abilities of procedures and data for common storages, but also provide the ability of processing the data in the storages. Further, the device has the advantages of high performance, low power consumption and convenient application.

Description

technical field [0001] The patent of the present invention relates to a memory of a data processing system, in particular to a DRAM (Dynamic Random Access Memory) device with data processing capability. Background technique [0002] Over the past few decades, processor performance has been doubling every 18 months in accordance with Moore's Law. This is all due to the huge improvement of integrated circuit manufacturing process and architecture technology. However, people have also begun to realize that there are more and more factors hindering the further improvement of the performance of the processor. Among them, the "storage wall" is a difficult problem in the existing Von Neumann architecture. In previous designs and productions, processors and memories were designed and optimized independently. The manufacturing process of the processor is aimed at producing fast logic; and the manufacturing process of the memory DRAM is aimed at obtaining storage density. Therefor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/401G11C11/4063G06F13/16
CPCY02B60/1235Y02B60/1228Y02D10/00
Inventor 戴葵
Owner 戴葵