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Method for correcting layout design for correcting metallic coating of contact hole

A metal overlay, layout design technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as misalignment of key dimension changes, and achieve the effect of pattern outline optimization and simple operation

Inactive Publication Date: 2010-02-24
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Aiming at the current problems such as critical dimension variation and misalignment that are prone to occur when making metal-covered contact holes or through-hole structures due to the shrinkage of design rules, the present invention is proposed

Method used

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  • Method for correcting layout design for correcting metallic coating of contact hole
  • Method for correcting layout design for correcting metallic coating of contact hole
  • Method for correcting layout design for correcting metallic coating of contact hole

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] Layout design corrections for overlay metal lines

[0030] Figure 2a Shown is the positional relationship between the contact hole or via hole pattern 2 and the cover layer metal pattern 1 in the original layout design, the metal line width L=240nm, the line spacing N=240nm, the edge of the contact hole pattern 2 and the metal line pattern 1 with an edge spacing of 10nm.

[0031] For the contact hole pattern, enlarge each side using the magnification value calculated by the following formula:

[0032] Amplification value E = ( a ) 2 + ( b ) 2 + ( c ) 2

[0033] Among them, a represents the metal critical dimension variati...

Embodiment 2

[0036] Process from Corrected Layout Design to Lithographic Results

[0037] Such as Figure 3a As shown, in the original layout, the contact hole pattern 2 is located at the line end of the cover layer metal line pattern 1, 55nm away from the edge of the line end, and other data are the same as in Example 1;

[0038] According to the calculated value, each side of the contact hole pattern is expanded by 50nm, such as Figure 3b As shown, the contact hole pattern is 5nm away from the edge of the line end after correction;

[0039] Then perform Boolean logic operation of "OR" on the expanded contact hole pattern 2 and the original metal circuit layer pattern 1 to obtain a complementary integrated layout of the two layer patterns, which is used as the metal layer pattern.

[0040] Taking the obtained metal layer pattern as the target of optical approximation correction, the layout is subjected to optical approximation correction, and the result is as follows Figure 3c As sho...

Embodiment 3

[0043] Comparison of metal-covered contact hole pattern profiles formed by the prior art and the scheme of the present invention

[0044] attached Figure 4a with 5a The diagrams respectively show the pattern outlines of several contact holes that cannot be aligned with the covering metal layer after photolithography of the pattern features on the silicon wafer in practical applications, resulting in partial exposure outside the metal covering layer. Figure 4b with Figure 5bThe outline schematic diagrams of photolithography of pattern features onto silicon wafers are respectively shown after the layout is corrected according to the scheme of the present invention. In the figure, numeral 3 represents the contour line of the metal line area actually formed after photolithography; numeral 4 represents the contour line of the contact hole pattern actually formed after photolithography. It can be clearly seen that for the same layout design, after being corrected by the method...

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Abstract

The invention provides a method for modifying a pattern of a circuit layer covering contact hole in multilayered integrated circuit layout design. When design rules of the integrated circuit are shrunk, manufacture of an ideal pattern of the circuit metal layer covering contact hole or a circuit metal layer covering through hole is very difficult as for the multilayered integrated circuit structure because the size of devices is reduced. Sometimes, the through hole or the contact hole can not be in alignment with a circuit and be exposed out of the metal circuit. The invention provides a method for politically amplifying the size of the pattern of the metal circuit layer covering contact hole. By utilization of the method to modify the circuit layer pattern and then perform optical approximate correction on the circuit layer pattern so as to manufacture a mask, a better pattern outline can be obtained through photoetching on a wafer, thereby the problems are completely avoided.

Description

technical field [0001] The invention relates to the layout design and photolithography process in the semiconductor manufacturing industry, and in particular to a method for correcting the layout design of the metal covering layer of the contact hole to reduce the variation of critical dimensions and misalignment. Background technique [0002] The semiconductor device is a multi-layer circuit stacked structure, and there is a via layer between adjacent circuit structure layers, in which there are multiple square or rectangular through holes filled with metal plugs to keep the circuits on the upper and lower layers electrically connected , the top layer circuit is connected to the outside world through the contact layer (Contact layer) which is similar in structure to the through hole layer. The through holes or contact holes can be collectively referred to as contact holes, and their function is to keep the circuits of each layer connected to each other. This structure requi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L27/02G06F17/50
Inventor 洪齐元
Owner SEMICON MFG INT (SHANGHAI) CORP