Method for correcting layout design for correcting metallic coating of contact hole
A metal overlay, layout design technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as misalignment of key dimension changes, and achieve the effect of pattern outline optimization and simple operation
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Embodiment 1
[0029] Layout design corrections for overlay metal lines
[0030] Figure 2a Shown is the positional relationship between the contact hole or via hole pattern 2 and the cover layer metal pattern 1 in the original layout design, the metal line width L=240nm, the line spacing N=240nm, the edge of the contact hole pattern 2 and the metal line pattern 1 with an edge spacing of 10nm.
[0031] For the contact hole pattern, enlarge each side using the magnification value calculated by the following formula:
[0032]
[0033] Among them, a represents the metal critical dimension variation value; b represents the critical dimension variation value of the contact hole or via; c represents the misalignment specification between the contact hole or via hole and the edge of the metal line; these three values are actually each The error allowed for each layer of the technology node. For example, for a metal line layer with a design size of 170 nanometers, the allowable error is 10%,...
Embodiment 2
[0036] Process from Corrected Layout Design to Lithographic Results
[0037] Such as Figure 3a As shown, in the original layout, the contact hole pattern 2 is located at the line end of the cover layer metal line pattern 1, 55nm away from the edge of the line end, and other data are the same as in Example 1;
[0038] According to the calculated value, each side of the contact hole pattern is expanded by 50nm, such as Figure 3b As shown, the contact hole pattern is 5nm away from the edge of the line end after correction;
[0039] Then perform Boolean logic operation of "OR" on the expanded contact hole pattern 2 and the original metal circuit layer pattern 1 to obtain a complementary integrated layout of the two layer patterns, which is used as the metal layer pattern.
[0040] Taking the obtained metal layer pattern as the target of optical approximation correction, the layout is subjected to optical approximation correction, and the result is as follows Figure 3c As sho...
Embodiment 3
[0043] Comparison of metal-covered contact hole pattern profiles formed by the prior art and the scheme of the present invention
[0044] attached Figure 4a with 5a The diagrams respectively show the pattern outlines of several contact holes that cannot be aligned with the covering metal layer after photolithography of the pattern features on the silicon wafer in practical applications, resulting in partial exposure outside the metal covering layer. Figure 4b with Figure 5bThe outline schematic diagrams of photolithography of pattern features onto silicon wafers are respectively shown after the layout is corrected according to the scheme of the present invention. In the figure, numeral 3 represents the contour line of the metal line area actually formed after photolithography; numeral 4 represents the contour line of the contact hole pattern actually formed after photolithography. It can be clearly seen that for the same layout design, after being corrected by the method...
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