Semiconductor device and a method of manufacturing the same

[0050] Hereinafter, the embodiments of the present invention will be explained with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals and symbols are used for the same elements in principle, and repeated descriptions thereof are omitted.

[0051] 1 is a cross-sectional view showing relevant parts of a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory according to an embodiment, and FIG. 2 is a view of the MONOS type nonvolatile memory shown in FIG. Equivalent circuit diagram. Figures 1 and 2 show two memory cells (MC1, MC2) arranged adjacent to each other.

[0052] A memory cell MC1 as a MONOS type nonvolatile memory is formed at a p-type well 2 in a semiconductor substrate 1 (hereinafter, simply referred to as "substrate") made of a p-type single crystal silicon substrate or the like. The p-type well 2 is electrically separated from the substrate 1 by an n-type embedded layer 4 for well isolation, wherein a desired voltage is applied to the p-type well 2.

[0053] The memory cell MC1 includes a control transistor C1 and a memory transistor M1. The gate electrode (control gate 8) of the control transistor C1 includes an n-type polysilicon film, and is formed over the gate insulating film 6 made of a silicon oxide film or the like. The gate electrode (storage gate 9) of the memory transistor M1 includes an n-type polysilicon film, which is provided at one sidewall of the control gate 8. The storage gate 9 is electrically separated from the control gate 8 and the p-type well 2 by a charge storage layer 16 having an L-shaped cross section. A part of the charge storage layer 16 is formed at one sidewall of the control gate 8 and the other part It is formed above the p-type well 2. The charge storage layer 16 includes two silicon oxide films and a silicon nitride film formed between the two silicon oxide films. When data is written, hot electrons generated at the channel region are injected into the charge storage layer 16 and are trapped at the traps in the silicon nitride film.

[0054] N used as the drain region of the memory cell MC1 + The type semiconductor region 10d is formed in the p-type well 2 adjacent to the control gate 8. Similarly, n used as the source region of the memory cell MC1 + The type semiconductor region 10s is formed in the p-type well 2 adjacent to the storage gate 9.

[0055] Relative to n + Type semiconductor region 10d has a lower impurity concentration n - Type semiconductor region 11d is formed in + In the p-type well 2 in a region adjacent to the type semiconductor region (drain region) 10d. That is, the n - Type semiconductor region 11d and n as a high-concentration diffusion layer + Type semiconductor region 10d. n - Type semiconductor region 11d is used to reduce + The high electric field at the end portion of the type semiconductor region (drain region) 10d makes the control transistor C1 an extended region of the LDD (lightly doped drain) structure.

[0056] Relative to n + Type semiconductor region 10s has a lower impurity concentration n - Type semiconductor region 11s is formed in + In the p-type well 2 in the region adjacent to 10s of the type semiconductor region (source region). That is, the n - Type semiconductor region 11s and n as a high-concentration diffusion layer + Type semiconductor region 10s. n - Type semiconductor region 11s is used to reduce the + The high electric field at the end portion of the type semiconductor region (source region) 10s makes the memory transistor M1 an extended region of the LDD structure.

[0057] A sidewall spacer 12 including a silicon oxide film is formed at the other sidewall of the control gate 8 and at one sidewall of the storage gate 9. Use sidewall spacers 12 to form n + Type semiconductor region (drain region) 10d and n + Type semiconductor region (source region) 10s.

[0058] The data line DL is formed by the silicon nitride film 20 and the silicon oxide film 21 on the memory cell MC1 configured as above. The data line DL is formed at n + Type semiconductor region (drain region) 10d above the contact hole 22 plug 23 and electrically coupled to n + Type semiconductor region (drain region) 10d. The data line DL is made of a metal film including aluminum alloy as a main component, and the plug 23 is made of a metal film including tungsten as a main component.

[0059] As shown in FIG. 2, the control gate 8 of the control transistor C1 is coupled to the control gate line CGL0, and the storage gate 9 of the storage transistor M1 is coupled to the storage gate line MGL0. The source region 10s is coupled to the source line SL, and a power supply line, not shown, applies a desired voltage to the p-type well 2.

[0060] The memory cell MC2 adjacent to the memory cell MC1 is arranged in the same structure as the memory cell MC1, and its drain region 10d and the drain region 10d of the memory cell MC1 are common. As described above, the drain region 10d is coupled to the data line DL. The two memory cells MC1 and MC2 are arranged symmetrically to each other and sandwich a common drain region 10d. The control gate 8 of the control transistor C2 is coupled to the control gate line CGL1 and the storage gate 9 of the storage transistor M2 is coupled to the storage gate line MGL1. The source region 10s is coupled to the source line SL.

[0061] The corresponding operations of writing, erasing, and reading when the memory cell MC1 is the selected memory cell will be explained later. In this case, the injection of electrons into the charge storage layer 16 is defined as "writing", and the injection of holes is defined as "erasing".

[0062] As the writing method, a hot electron writing method called a source side injection method is used. When writing, apply 0.7V to the control gate 8, 10V to the storage gate 9, 6V to the source region 10s, 0V to the drain region 10d, and 0V to the p-type Well 2. Thus, hot electrons are generated in the vicinity of the middle region between the control gate 8 and the storage gate 9 in the channel region formed between the source region 10s and the drain region 10d, which are injected into the charge storage layer 16. . The injected electrons are captured by traps in the silicon nitride film, thereby increasing the threshold voltage of the memory transistor M1.

[0063] As the erasing method, a hot hole injection erasing method using channel current is used. When erasing, apply 0.7V to the control gate 8, -8 V to the storage gate 9, 7V to the source region 10s, 0V to the drain region 10d, and 0V to the p-type well 2. Thus, a channel region is formed at the p-type well 2 under the control gate 8. Since a high voltage (7V) is applied to the source region 10s, the depletion layer extending from the source region 10s is close to the channel region of the control gate C1. As a result, the electrons flowing through the channel region are accelerated by the high electric field between the end portion of the channel region and the source region 10s to cause collision ionization, thereby generating electron-hole pairs. The holes are accelerated by the negative voltage (-8V) applied to the storage gate 9 to become hot holes injected into the charge storage layer 16. The injected holes are trapped in the silicon nitride film, thereby reducing the threshold voltage of the memory transistor M1.

[0064] When reading, apply 1.5V to the control gate 8, 1.5V to the storage gate 9, 0V to the source region 10s, 1.5V to the drain region 10d, and 0V to the p-type well 2. That is, the voltage applied to the storage gate 9 is set between the threshold voltage of the memory transistor M1 in the writing state and the threshold voltage of the memory transistor M1 in the erasing state, which is different from the writing state and the erasing state. State distinction.

[0065]Next, the manufacturing method of the MONOS-type nonvolatile memory will be explained in the process sequence with reference to FIGS. 3 to 18. As the peripheral circuit of the MONOS type nonvolatile memory, for example, there are sense amplifiers, column decoders, row decoders, and boost circuits. Thus, a memory array region in which a memory cell is formed, a low withstand voltage MIS region in which a low withstand voltage MISFET is formed, a high withstand voltage MIS region in which a high withstand voltage MISFET is formed, and a source/drain region in which it is formed are designated Used in the MIS area of ​​the MISFET with high withstand voltage and the capacitor area in which the MIS capacitor is formed.

[0066] First, as shown in FIG. 3, by using a well-known manufacturing method, the n-type embedded layer 4 and the p-type well 2 are formed over the main surface of the substrate 1 in the memory array region, and the p-type well 2 is formed on the periphery. Above the main surface of the substrate 1 in the circuit. Next, by thermally oxidizing the substrate 1, a gate insulating film 7 including silicon oxide is formed over the surface of the p-type well 2.

[0067] Subsequently, as shown in FIG. 4, after removing the gate insulating film 7 in the memory array region, the low withstand voltage MIS region, and the MIS region by using photolithography technology and etching technology, the substrate 1 is thermally oxidized to remove A gate insulating film 6 including silicon oxide is formed above the p-type well 2. That is, the gate insulating film 6 is formed over the main surface of the substrate 1 in the memory array area, the low withstand voltage MIS area, and the MIS area, and the gate insulating film in the capacitor area and the high withstand voltage MIS area is thickened.膜7。 Film 7.

[0068] By repeating the process of the gate insulating film (oxidation/removal process described with reference to FIGS. 3 and 4), a gate insulating film having a plurality of film thicknesses can be formed. In the embodiment, the gate insulating film 6 in the memory array region, the low withstand voltage MIS region, and the MIS region are formed in the same process, and the film thickness is about 3 to 4 nm. The gate insulating film 7 in the high withstand voltage MIS region and the capacitor region is formed in the same process, and the film thickness is about 7 to 8 nm.

[0069] As described above, the gate insulating film 6 is formed in the memory array area, the low withstand voltage MIS area, and the MIS area, and the gate insulating film 7 is formed in the high withstand voltage MIS area and the capacitance area. The gate insulating film 7 is formed to have a thicker film thickness (approximately 7 to 8 nm) than that of the gate insulating film 6 (approximately 3 to 4 nm) to ensure withstand voltage. That is, the gate insulating film 6 in the memory array region and the gate insulating film 6 in the low withstand voltage MIS region are the same film formed in the same process. As described below, the gate insulating film 6 in the memory array area will become the gate insulating film of the control gate 8. Therefore, it is not the gate insulating film 7 in the high withstand voltage MISFET, but the gate insulating film 6 in the low withstand voltage MISFET becomes the gate insulating film of the control gate 8, which enables the memory cell to operate at high speed.

[0070] Subsequently, as shown in FIG. 5, after depositing an electrode material film 8A made of an undoped (impurity doping not performed) silicon film having a film thickness of about 150 nm over the substrate 1 by the CVD method, The CVD method deposits a thin silicon oxide film (not shown) thereon for protecting the surface of the electrode material film 8A.

[0071] Subsequently, by using a photolithography technique, a predetermined area is masked with a photoresist film, and impurities (phosphorus or arsenic) are ion-implanted into the electrode material film 8A, thereby forming the electrode material film 8A made of an undoped silicon film. The unmasked area in the middle becomes a doped n-type silicon film. In this case, the impurity is phosphorus and its dosage is about 6×10 16 /cm 2.

[0072] Subsequently, as shown in FIG. 6, a cap insulating film 41 made of a silicon oxide film or the like for gate processing is deposited over the electrode material film 8A by a CVD method.

[0073] Subsequently, as shown in FIG. 7, the cap insulating film 41 in the memory array area, the high withstand voltage MIS area, and the MIS area is removed by using photolithography and etching techniques, so that the cap insulating film 41 remains in the low withstand voltage MIS. Area and capacitance area.

[0074] Subsequently, as shown in FIG. 8, an electrode material film 8B made of an undoped silicon film with a film thickness of about 100 nm is deposited over the electrode material film 8A by a CVD method to cover the cap insulating film 41. After that, the electrode material film 8B made of an undoped silicon film is changed to an n-type silicon film. Although this is performed in the same manner as the electrode material film 8A including the undoped silicon film is changed to the n-type silicon film, in the embodiment, as described below, the change is performed by forming the semiconductor region (extended region) And source/drain regions) are performed by ion implantation of impurities into the substrate 1.

[0075] Subsequently, as shown in FIG. 9, while protecting the electrode material film 8A in the low withstand voltage MIS region and the capacitor region with the cap insulating film 41, the electrode material film 8B and the electrode material film 8B and the electrode material film are treated by photolithography and etching techniques. 8A is patterned (dry etching). Thus, in the memory array region, a control gate 8 including an electrode material film 8B as an undoped silicon film and an electrode material film 8A as an n-type silicon film is formed. In the high withstand voltage MIS region and the MIS region, a gate electrode 15 including an electrode material film 8B as an undoped silicon film and an electrode material film 8A as an n-type silicon film is formed. In the gate processing conditions of this process, the cap insulating film 41 cannot be removed, and therefore, the electrode material film 8A in the low withstand voltage MIS region and the capacitance region remains in a self-aligned manner.

[0076] In a later process, impurity ions are implanted into the gate electrode 15 and the control gate 8 including the electrode material film 8B as an undoped silicon film, so that the electrode material film 8B becomes an n-type silicon film. Thus, since the gate electrode 15 in the peripheral circuit and the control gate 8 in the memory cell can be formed at the same time using the undoped silicon film, the gate formation process can be simplified.

[0077] The gate length of the control gate 8 formed in the memory array area is about 180 nm. When the gate length of the control gate 8 is as short as about 180 nm, the aspect ratio (the ratio of the height (thickness) of the control gate 8 to the gate length) is greater than one. Therefore, a storage gate 9 having a gate length smaller than that of the control gate 8 can be formed at the sidewall of the control gate 8.

[0078] Subsequently, as shown in FIG. 10, the cap insulating film 41 in the capacitance region and the low withstand voltage MIS region is removed.

[0079] Subsequently, as shown in FIG. 11, the electrode material film 8B and the electrode material film 8A are patterned (dry etching) using a photolithography technique and an etching technique. Thus, the gate electrode 14 including the electrode material film 8A as the n-type silicon film is formed in the low withstand voltage MIS region and the capacitance region.

[0080] By repeating the gate process (the process described with reference to FIGS. 6 to 11), a gate electrode having multiple heights (film thicknesses) can be formed. In this embodiment, with a stacked structure of the electrode material film 8A and the electrode material film 8B, the control gate 8 in the memory array region and the gate electrode 15 in the high withstand voltage MIS region and the MIS region are formed with a film thickness ( Height) is about 250nm. The gate electrode 14 in the low withstand voltage MIS region and the capacitor region is formed with a single-layer structure of the electrode material film 8A, and the film thickness is about 150 nm.

[0081] Subsequently, as shown in FIG. 12, the unnecessary gate insulating film 6 in the memory cell region, the low withstand voltage MIS region, and the MIS region is removed by patterning, and the gate insulating film 6 is allowed to remain on the control gate 8 of the memory cell region. Below, below the gate electrode 14 in the low withstand voltage MIS region, and below the gate electrode 15 in the MIS region.

[0082] Next, the charge storage layer 16 is formed over the substrate 1. That is, the charge storage layer 16 is formed to cover the main surface of the substrate 1 and the sidewalls and top surface of the control gate 8.

[0083] The charge storage layer 16 is formed by an ONO (Oxide Nitride Oxide) film, which includes three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The silicon oxide film at the lower layer of these three layers is formed by a thermal oxidation method or a CVD method. Also preferably, the film can also be formed using an ISSG (In-Situ Steam Generation) oxidation method, in which hydrogen and oxygen are introduced into the chamber of the thermal oxidation device to perform a radical oxidation reaction above the heated wafer. The silicon nitride film is formed by the CVD method or the ALD (Atomic Layer Deposition) method, and the silicon oxide film on the upper layer is formed by the CVD method or the ISSS oxidation method. After forming the silicon oxide film of the lower layer, and before forming the silicon nitride film, including N 2 The silicon oxide film is nitridated in a high temperature atmosphere of O oxynitride, thereby isolating nitrogen at the interface between the silicon oxide film and the substrate 1 (p-type well 2). By performing the nitridation treatment, the hot carrier resistance of the control transistor and the memory transistor included in the memory cell is improved, and as a result, the characteristics of the memory cell (such as rewriting characteristics) are improved.

[0084] Prior to the process of forming the charge storage layer 16 after the control gate 8 is formed, impurities for adjusting the threshold voltage of the control transistor or impurities for adjusting the threshold voltage of the memory transistor are preferably ion-injected into the p-type well in the memory array region. 2 in. Therefore, the threshold voltages of the control transistor and the storage transistor can be optimized.

[0085] Next, an electrode material film 9A made of an n-type polysilicon film or the like is formed over the substrate 1 by a CVD method. Compared with the case of ion implantation of impurities after deposition, a so-called doped polysilicon film (n-type polysilicon film) in which impurities are introduced at the time of deposition can reduce resistance.

[0086] Subsequently, as shown in FIG. 13, the electrode material film 9A is anisotropically etched to allow the electrode material film 9A made of an n-type polysilicon film or the like to be in the control gate 8, the gate electrodes 14 and 15 in the peripheral circuit.的 corresponding two side walls. The impurity (phosphorus or arsenic) concentration of the n-type polysilicon film is about 1×10 20 /cm 3 To 6×10 20 /cm 3.

[0087] Subsequently, as shown in FIG. 14, using a photoresist film (not shown) covering the storage gate formation region as a mask, the electrode material film 9A made of an n-type polysilicon film or the like is etched. Thus, the storage gate 9 including the electrode material film 9A is formed at one sidewall of the control gate 8.

[0088] The gate length of the storage gate 9 formed at the sidewall of the control gate 8 is about 80 nm, and its aspect ratio (ratio of height (thickness) to gate length) is greater than one. In this embodiment, since the storage gate 9 is formed after the control gate 8 is formed, the storage gate 9 having a high aspect ratio in which the gate length is further smaller than the control gate 8 can be easily formed.

[0089] Next, the three-layer insulating film forming the charge storage layer 16 is etched using hydrofluoric acid and phosphoric acid. Thus, the charge storage layer 16 formed at an unnecessary area is removed, so that the charge storage layer 16 remains only at one sidewall of the control gate 8 and under the storage gate 9.

[0090] Subsequently, as shown in FIG. 15, by using the gate electrode 14 and a photoresist film (not shown) as a mask, an impurity (phosphorus or arsenic) is ion-implanted into the low withstand voltage MIS region and the capacitor region to form n - Type semiconductor region 17. n - The type semiconductor region 17 is an extended region for making the n-channel low withstand voltage MISFET and the MIS capacitor have an LDD structure.

[0091] Next, by using the gate electrode 15 and a photoresist film (not shown) as a mask, an impurity (phosphorus or arsenic) is ion-implanted into the high withstand voltage MIS region and the MIS region to form n - Type semiconductor region 24. n - The type semiconductor region 24 is an extended region for making the n-channel high withstand voltage MISFET and the MISFET whose source/drain regions are designated for high withstand voltage become an LDD structure. In the formation of n -At the same time as the process of the type semiconductor region 24, impurities (phosphorus or arsenic) are ion-implanted into the electrode material film 8B made of an undoped silicon film, thereby forming an electrode made of a doped n-type silicon film. Material film 8B.

[0092] Used to form n - Type semiconductor region 17 and n - The ion implantation of the type semiconductor region 24 may be performed before the charge storage layer 16 is removed, however, in order to form a shallow pn junction, it is advantageous to perform the ion implantation after the charge storage layer 16 is removed.

[0093] Subsequently, as shown in FIG. 16, using a separation gate including the control gate 8 and the storage gate 9 and a photoresist film (not shown) as a mask, an impurity (phosphorus) is ion-implanted into the storage array region. Or arsenic) to form n - Type semiconductor regions 11d and 11s. n - The type semiconductor regions 11d and 11s are extended regions for making the memory cell an LDD structure.

[0094] Thereafter, as shown in FIG. 19, it is preferable to pass to n - The p-type impurity (boron or boron difluoride) is ion-implanted (halo implantation) into the type semiconductor region 11 s to form the p-type semiconductor region 42. In this case, n on the source side - A p-type semiconductor region 42 is formed under the type semiconductor region 11s and serves as a region (halo region) for suppressing the short channel effect of the memory cell. As shown in FIG. 20, compared with the case where the p-type semiconductor region 42 is not formed in the case where there is no halo region, the memory cell MC such as shown in FIG. In the case of the type semiconductor region 42, the writing level (current level) of the threshold voltage of the memory cell MC is increased. Therefore, by adding a halo area to the source of the memory cell MC, the electric field at the source terminal is increased, the injection of channel hot electrons is increased, the short channel effect is improved and the subthreshold coefficient is reduced, thereby increasing Write speed. In FIG. 20, the erase time with respect to the threshold voltage of the memory cell MC is shown. That is, through n on the source side - Forming a p-type semiconductor region under 11s of the type semiconductor region can improve the write level without reducing the level of erasing time.

[0095] Subsequently, as shown in FIG. 17, a sidewall spacer 12 is formed at each sidewall of the control gate 8 and the storage gate 9 formed in the memory array region, and the sidewall spacer 12 is formed in the peripheral circuit region The gate electrode 14 and the gate electrode 15 in the corresponding sides. This sidewall spacer 12 is formed by etching back (anisotropic etching) an insulating film made of a silicon oxide film or the like deposited on the substrate 1 by a CVD method.

[0096] Subsequently, as shown in FIG. 18, using a photoresist film (not shown) as a mask, impurities (phosphorus or arsenic) are ion-implanted into the memory array area and the peripheral circuit area. And used to form the extended area (n - Compared with the ion implantation of the semiconductor regions 11s, 11d, 17 and 24), the ion implantation has a higher impurity dose (about 1×10 13 /cm 2 ) And higher injection energy (about 40KeV).

[0097] According to the above content, in the memory array area, the separation gate and the sidewall spacer 12 are used as masks to form n in the vicinity of the separation gate. + Type semiconductor region (drain region) 10d and n + Type semiconductor region (source region) 10s to complete the memory cell MC. In the low withstand voltage MIS area and the capacitor area, the gate electrode 14 and the sidewall spacer 12 are used as masks, and n is formed in the vicinity of the gate electrode 14 + Type semiconductor region 26 completes the n-channel type low withstand voltage MISFET (Q1) and MIS capacitor (C). In the high withstand voltage MIS region and the MIS region, the gate electrode 15 and the sidewall spacer 12 are used as masks to form n + The type semiconductor region 27 completes the n-channel type high withstand voltage MISFET (Q2) and its source/drain are designated for the high withstand voltage MISFET (Q3).

[0098] In the memory array area, a separate gate including the control gate 8 and the storage gate 9 is used as a mask, and the n is implanted by impurity (phosphorus or arsenic) ion implantation. - The semiconductor regions 11 s and 11 d are formed above the main surface of the substrate 1. The sidewall spacer layer 12 is formed at the sidewall of the separation gate, and using the separation gate and the sidewall spacer layer 12 as a mask, is formed over the main surface of the substrate 1 by ion implantation of impurities (phosphorus or arsenic) Than n - The semiconductor regions 11s and 11d have higher impurity concentration n + Type semiconductor regions 10s and 10d. Since the ratio (aspect ratio) of the height (thickness) of the storage gate 9 to the gate length of the storage gate 9 is greater than 1, it is possible to ensure the width (along the substrate 1) under the sidewall spacer 12 formed in the above process. size of). Therefore, the n formed in the above process can be suppressed + Leakage (junction leakage) occurs at the junction between the type semiconductor regions 10s, 10d and the p-type well 2.

[0099] Since it is used to form n + Impurities are also injected into the control gate 8 and the gate electrode 15 during the ion implantation process of the type semiconductor regions 10s, 10d, and 27, so the electrode material film 8B forming the control gate 8 and the gate electrode 15 is changed from an undoped silicon film. It is a low resistance n-type silicon film. Therefore, the process of ion implanting impurities into the electrode material film 8B for forming the control gate 8 and the gate electrode 15 and the photomask to be used in the process can be omitted. However, for example, impurities are also ion-implanted into the n-channel type low withstand voltage MISFET (Q1), etc., and therefore, it is necessary to consider changes in its characteristics.

[0100] Used to form n + In the ion implantation process of the type semiconductor regions 10s and 10d, impurities are also implanted into the control gate 8 and the storage gate 9. And used to form n - Compared with the ion implantation of the type semiconductor regions 11s and 11d, this ion implantation has a higher impurity dose and a higher implantation energy. Therefore, in the case where the height (thickness) of the control gate 8 or the storage gate 9 is insufficient, when the impurity injected into the control gate 8 or the storage gate 9 passes through the gate insulating film 6 or charge under these gates When the storage layer 16 reaches the surface of the p-type well 2, the threshold voltage of the control transistor or the storage transistor changes.

[0101] As described above, with the miniaturization of the gate electrode (gate length), it is necessary to make the gate electrode thinner to ensure the ratio (aspect ratio) of the height (thickness) of the gate electrode to the gate length. Therefore, in the semiconductor device including the memory array and its peripheral circuits shown by the state of this embodiment, the thickness of the gate electrode 14 in the low withstand voltage MISFET (Q1) is made thinner for miniaturization.

[0102] However, for example, in the case where the gate electrode 14 in the low withstand voltage MISFET (Q10) and the control gate 8 of the memory cell MC0 are formed at the same time, such as in the technique described by the present inventor with reference to FIGS. 21 and 22, when When the gate electrode 14 is made thinner, the control gate 8 is also made thinner. In this case, when used to form n + In the ion implantation process of the type semiconductor regions 10s, 10d, impurities are also injected into the control gate 8 or the storage gate 9 and pass through the gate insulating film 6 or the charge storage layer 16 under these gates to reach the p-type well. 2 surface, the threshold voltage of the control transistor or memory transistor changes.

[0103] In the present invention, the gate electrode 14 is made into a single-layer structure including the electrode material film 8A of the control gate 8 to be miniaturized, and the control gate 8 is made into a structure including the electrode material film 8A and the electrode material film 8B. The multilayer structure is such that its height (thickness) is higher than that of the gate electrode 14, thereby preventing impurities from passing through during ion implantation. Thus, the change in threshold voltage can be suppressed in the nonvolatile memory, and problems such as failure of the nonvolatile memory can be prevented from occurring.

[0104] Subsequently, after the silicon nitride film 20 and the silicon oxide film 21 are deposited over the substrate 1 by the CVD method, the data line DL is formed over the silicon oxide film 21 in the memory array area, and is connected to the data line DL The wiring in the same layer is formed above the peripheral circuit area (refer to Figure 1). After that, a plurality of wirings are formed at the data line DL and the upper layer of the wiring, although not shown, an interlayer insulating film is sandwiched between them.

[0105] It is also possible to form the silicon nitride film 20 over the surface of the drain region 10d, the source region 10s, the storage gate 9, and the control gate 8 in the memory cell MC before the process of forming the silicon nitride film 20 over the substrate 1. A silicide layer such as cobalt silicide makes the control gate 8 and the storage gate 9 low resistance. Similarly, the n in the peripheral circuit + A silicide layer including cobalt silicide or the like is formed on the surfaces of the type semiconductor regions 26 and 27 and the gate electrodes 14 and 15.

[0106] For example, in the memory cell MC, another sidewall spacer is formed by the sidewall spacer 12 at the sidewall of the separation gate, and one end of the silicide layer is formed in the vicinity of the other sidewall spacer. At n + Type semiconductor regions 10s, 10d, that is, the silicide layer is not formed on the n - Above the type semiconductor regions 11s and 11d. Since the ratio (aspect ratio) of the thickness of the storage gate 9 to the gate length of the storage gate 9 is greater than 1, the width (along the size of the substrate 1) under the sidewall spacer 12 formed in the above process can be ensured In addition, the width under the other sidewall spacer formed by the sidewall spacer 12 can also be ensured. Therefore, it can be suppressed to n + Leakage (junction leakage) occurs at the junction between the silicide layer formed over the type semiconductor regions 10s and 10d and the p-type well 2.

[0107] For example, the silicide layer of the memory cell MC is formed by the following process. First, after a silicon oxide film is formed to cover the main surface of the substrate 1, the top surface and the sidewalls of the separation gate, the silicon oxide film is etched back to form a sidewall spacer at the sidewalls of the separation gate. Next, a metal film (for example, a titanium film) is formed to cover the main surface of the substrate 1, the top surface and the sidewalls of the separation gate, and the n + The contact portions of the type semiconductor regions 10s, 10d and the metal film are silicided, thereby forming a silicide layer (for example, a titanium silicide film) whose one end is provided near the sidewall spacer. After that, the unreacted metal film is removed.

[0108] As described above, the present invention made by the inventor has been specifically explained based on the embodiments, and it goes without saying that the present invention is not limited to these embodiments, but various modifications can be made within the scope not departing from the spirit of the present invention .

[0109] For example, in the embodiment, the case where the present invention is applied to five types of semiconductor elements, namely, a memory cell, a low withstand voltage MISFET, a high withstand voltage MISFET, and a MISFET whose source/drain region is a high withstand voltage As well as the MIS capacitor, however, the present invention can be applied to semiconductor devices each having gate insulating films of multiple thicknesses and gate electrodes of multiple heights.

[0110] In the above-mentioned embodiment, the case where the n-channel type MISFET is used is explained, however, for example, the case where the p-channel type MISFET is used is also preferable. At this time, the electrode material film 8A made of an undoped silicon film may be a p-type silicon film. For example, by using a photolithography technique, a predetermined area is masked with a photoresist film, and impurities (boron or boron difluoride) are ion-implanted into the undoped silicon film 8A, thereby making an undoped silicon film The unmasked area in the electrode material film 8A becomes a p-type silicon film. Thus, n-type or p-type pre-doping can be performed, and as a result, device characteristics can be effectively improved.

[0111] The present invention can be widely used in the manufacturing industry of manufacturing semiconductor devices.