Semiconductor device and a method of manufacturing the same

Abstract

In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8 A and an electrode material layer 8 B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8 A of the control gate.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2006-131208 filed on May 10, 2006 including specification, drawings and abstract is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to a semiconductor device and its manufacturing method, and more particularly, to a technique effective when applied to the manufacture of a semiconductor device including a nonvolatile memory and its peripheral circuits. Background technique [0004] As a nonvolatile memory (electrically erasable and programmable read-only memory) in which data can be rewritten electrically, a split gate type using a charge storage layer including an ONO (Oxide Nitride Oxide) film is known storage unit structure. [0005] As a peripheral circuit of a nonvolatile memory, for example, a circuit including a low withstand voltage MISFET such as a sense amplifier, a column decoder, and a row decoder, an...

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Problems solved by technology

Thereby, the size (width) of the underside of the sidewall spacer 12 along the gate length direction of the substrate 1 has been limited by the height of the separated grid, that is, the thickness of the control grid 8, so when the control grid 8 When the film thickness is made thin, it may be difficult to secure a sufficient width of the sidewall spacer 12

Thus, it is noted that in the n + The problem of junction leakage between the p-type semiconductor regions 10d, 10s and the p-type well 2 forming the junction surface

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