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Construction method and seven-value circuit of T-type network threshold-expansion any value general gate circuit

A construction method and gate circuit technology, which can be applied in the direction of logic circuits with logic functions, etc., can solve the problems of increasing ions, difficulty in applying multi-value circuits, and increasing process complexity.

Inactive Publication Date: 2007-11-28
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The shortcomings of the prior art to control the threshold of MOS tubes: ① the range of control threshold is limited (because the concentration of ion implantation is limited), and the resolution of opening is low; Leading to a sharp increase in the cut-off current, the adjustment of the threshold voltage has an impact on the performance and stability of the tube, and the stable V tn Very important
Therefore, the current practical voltage-type multi-valued circuit is not larger than the 4-valued circuit, and the application of more-valued circuits is more difficult
② Only the amplitude of the threshold value can be controlled, and the turn-on nature of the MOS tube cannot be changed (such as changing ≥t conduction to <t conduction), and the multi-valued logic gate must have two kinds of MOS tubes with turn-on properties to make the structure of the combination circuit the simplest , for example, the circuit structure of the seven-valued NOT gate, the seven-valued right shift gate and the seven-valued follower should be exactly the same, but the threshold voltage and its opening properties are different
However, the current technology that only controls the threshold amplitude makes the structure of the above-mentioned multi-valued gates very different and complicated, which affects its realization.
③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, which not only increases the complexity of the process, but also cannot be controlled by the user after the semiconductor manufacturing process, or the threshold is not programmable by the user

Method used

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  • Construction method and seven-value circuit of T-type network threshold-expansion any value general gate circuit
  • Construction method and seven-value circuit of T-type network threshold-expansion any value general gate circuit
  • Construction method and seven-value circuit of T-type network threshold-expansion any value general gate circuit

Examples

Experimental program
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Effect test

Embodiment 1

[0046] Embodiment 1: T-shaped network expanded threshold type seven-valued NOT gate circuit

[0047] In conjunction with FIG. 3, this embodiment uses 6 threshold-expanded NMOS transistors G i (i=1, 2, 3, 4, 5, 6), their gates are connected to input x through the threshold expansion circuit; tube G 1 The source is grounded, the other tubes G 2 ~G 6 The sources of all are connected to the lead wire g, and g has two connection methods: g grounding and g taking over G 1 The drain, the seven-value NOT gate selects g to ground; uses 5 diodes D i (i=1, 2, 3, 4, 5), diode D i The negative pole and positive pole of the gate are sequentially connected to the expanded threshold NMOS transistor G i The drain and expanded threshold NMOS transistor G i+1 Drain; threshold-expanded NMOS transistor G 6 The drain of the load is connected to the power supply V DD , and in the expanded-threshold NMOS tube G 6 The drain forms the seven-valued NOT gate output y. Expanded-threshold NMOS tr...

Embodiment 2

[0049] Embodiment 2: T-shaped network threshold expansion seven-valued right-shift gate circuit

[0050] Figure 4 and Figure 3 have the same structure, and the seven-valued right-sliding gate is G in Figure 4 1 ~G 6 The expanded threshold NMOS tube G i The normalized extended threshold value of i=1, 2, 3, 4, 5, 6 is sequentially taken as <4.5, <3.5, <2.5, <1.5, <0.5, ≥5.5.

[0051] Seven-valued right-sliding door requirements: when the input x is 6, 0, 1, 2, 3, 4, 5, the output z of the right-sliding door is 0, 1, 2, 3, 4, 5, 6 in sequence. Figure 4 Threshold Expanded NMOS Transistor G i The normalized extended thresholds of i=1, 2, 3, 4, 5, 6 are 6 Turn on, output z=0. ②When x=0, then x6 Cut off, G 5 and D 5 Conduction, output z=1; ③When x=1, then x5 , G 6 Cut off, G 4 and D 4 、D 5 Conduction, output z=2; ④When x=2, then x4 ~G 6 Cut off, G 3 and D 3 ~D 5 Conduction, output z=3; ⑤When x=3, then x3 ~G 6 Cut off, G 2 and D 2 ~D 5 Conduction, output z=4; ⑥When x...

Embodiment 3

[0052] Embodiment 3: T-shaped network expanded threshold type seven-valued follower circuit

[0053] Figure 6 and Figure 3 have the same structure, the seven-valued follower in Figure 6 G 1 ~G 6 The expanded threshold NMOS tube G i The normalized extended threshold of i=1, 2, 3, 4, 5, 6 is sequentially taken as <5.5, <4.5, <3.5, <2.5, <1.5, <0.5.

[0054] Seven-valued follower requirements: when the input x is 0, 1, 2, 3, 4, 5, 6, the output u is still 0, 1, 2, 3, 4, 5, 6 in turn. Figure 6 Threshold Expanded NMOS Transistor G i The normalized extended threshold of i=1, 2, 3, 4, 5, 6 is sequentially taken as 6 Conduction, output u=0; ②When x=1, then x6 Cut off, G 5 and D 5 Conduction, output u=1; ③When x=2, then x5 , G 6 Cut off, G 4 and D 4 、D 5 Conduction, output u=2; ④When x=3, then x4 ~G 6 Cut off, G 3 and D 3 ~D 5 Conduction, output u=3; ⑤When x=4, then x3 ~G 6 Cut off, G 2 and D 2 ~D 5 Conduction, output u=4; ⑥When x=5, then x2 ~G 6 Cut off, G 1 and D ...

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Abstract

The invention discloses a building method of all-purpose door circuit of T-shaped network expanding typed random value and six-value circuit, which is characterized by the following: setting random value all-purpose door circuit at K value (K equals 3, 4 and so on); adopting K-1=K' expanding typed NMOS pipe Gi (i=1, 2, 3 and so on); connecting the grid of expanding typed NMOS pipe Gi with the input x through threshold expanding circuit; connecting pipe G1 source electrode with ground and other pipe G2-GK' source electrodes with lead wire g; adopting K' -1 diodes Di (i=1, 2, 3.....,K'-1); connecting the anode and cathode of Di with the drain of expanding typed NMOS pipe Gi and the drain of expanding typed NMOS pipe Gi+1; connecting the drain of expanding NMOS pipe GK' with power VDD through load; connecting the drain of expanding typed NMOS pipe GK' with all-purpose door to output. The invention can expand to random K-value trigger and corresponding time-sequent circuit, which is fit for FPGA, CPLD, half or all-locking ASIC and memory and other digital IC technical domain.

Description

(1) Technical field [0001] The invention belongs to the technical field of digital integrated circuits, in particular to a method for constructing a T-shaped network threshold-expanding arbitrary-value general gate circuit. The general gate includes a NOT gate, a right-shift gate, a left-shift gate and a follower. (2) Technical background [0002] With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and higher, and the integration level is getting higher and higher. VLSI (Very Large Scale Integration) has some shortcomings. First, on the VLSI substrate, wiring takes up more than 70% of the silicon chip. Area; in programmable logic devices (such as FPGA and CPLD), there are also a large number of programmable internal wiring (including programmable connection switches, such as fuse switches, anti-fuse switches, floating gate programming components, etc.), the Each logic function block or input / output is connected to complete...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20
Inventor 刘莹方倩方振贤
Owner HEILONGJIANG UNIV
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