Semiconductor integrated circuit device and manufacturing method thereof

Abstract

The present invention provides a semiconductor integrated circuit device and the making method thereof. The semiconductor integrated circuit device can more effectively restrain the power supply noise of the whole of the semiconductor integrated circuit device and prevent the actuating speed reducing of the integrated circuit which is composed of the logic unit at the central part of the semiconductor integrated circuit device. The semiconductor integrated circuit forming area (11) is divided to a plurality of block areas with the mode comprising an electric power source main line (1) and the electric power line (3), a capacitor unit (5) is arranged at the vicinity of the electric power source of each divided block area, then a plurality of logic units are arranged at the area which is farther to the electric power source main line (1) comparing with the arranged capacitor unit (5). Besides, the number of the capacitor units (5) arranged in the block area is confirmed according to the voltage descending value of the electric power source line (3) of each divided block area.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device which reduces dynamic noise generated in a power supply main line and prevents abnormal operation and its manufacturing method. Background technique [0002] In recent years, semiconductor integrated circuit devices have increased power consumption per unit area as they have become more highly integrated, and may generate large power supply noise. On the other hand, power supply noise is generated due to a decrease in power supply voltage accompanying the miniaturization of processes, and the problem of reduced resistance to such power supply noise has become increasingly prominent. [0003] In order to solve this problem, not only the decoupling capacitor unit is inserted on the PCB (Printed Circuit Board, Printed Circuit Board) connecting the semiconductor integrated circuit devices, but also the capacitor unit is arranged on the empty area in the semiconductor integrated circ...

AI Technical Summary

Problems solved by technology

[0007] However, in the above-mentioned prior art, as shown in FIG. 6 , in a layout constructed in the order of the arrangement of logic cells (step S21), the arrangement of capacitor cells (step S22), and the arrangement of empty cells (step S23), In the configuration process of the design, the configuration of the capacitance unit on the semiconductor integrated circuit device (step S22) is carried out after disposing the logic unit (step S21), so the capacitance unit is arranged in the gap of the logic unit, in the area where the logic unit is densely packed There are few medium capacitor units, and more capacitor units are arranged in areas where logic units are sparse

In this case, for example, as shown in FIG. 7 , there are not enough capacitive units 65 near the area 67 where the logic units 66 that generate noise on the power rail 61 (62 represents the ground rail) are densely packed. As shown in FIG. 8 , in There is a distance before the power supply noise generated in the logic unit 66 reaches the capacitor unit 65, so the parasitic resistance 63 increases, and the decoupling effect decreases, and there is a problem that the power supply noise cannot be effectively reduced.

[0008] In addition, as for the capacitance unit, the capacitance unit whose area matches the gap of the logic unit is arranged, but if the area (size) of the arranged capacitance unit is small, the capacitance value per unit area (capacitance area ratio) cannot be increased

Therefore, when the gap between logic cells is small, only capacitor cells with small capacitance can be inserted, so decoupling capacitors cannot be set sufficiently, and there is a problem that power supply noise cannot be effectively reduced.

[0009] In addition, if the capacitive unit is arranged in the center of the semiconductor integrated circuit device in consideration of the voltage drop in the center of the semiconductor integrated circuit device, there is a problem that the power supply noise of the entire semiconductor integrated circuit device cannot be sufficiently reduced.

[0010] In addition, if the arrangement of the capacitance unit in the center of the semiconductor integrated circuit device is prioritized over the arrangement of the logic unit, unnecessary delays will occur in the integrated circuit composed of the logic unit in the center of the semiconductor integrated circuit device. The problem of slowing down of own movement speed

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