Semiconductor element and its forming method

Abstract

A semiconductor component of the invention comprises a semiconductor substrate; a grid stack which is arranged on the semiconductor substrate; a n-type light doped source/drain area which is arranged in the semiconductor and is stacked adjacent the grid, wherein the n-type light doped source/drain area comprises the n-type impurity; a n-type heavy doped source/drain area, wherein the n-type heavy doped source/drain area comprises the n-type impurity; a pre-amorphized implanting area which is arranged in the semiconductor substrate, wherein the pre-amorphized implanting area comprises a back implanting area; and a clearance blocking area, wherein the depth of the clearance blocking area is larger than the depth of the n-type light doped source/drain area but is less than the depth of the back implanting area. As the clearance blocking area of the invention is arranged between the back implanting area and the light doped source/drain area the problem of phosphorus diffusion in the light doped source/drain area can be reduced. Besides as the phosphorus has high activation rate the MOS element has low chip resistor.

Description

Technical field [0001] The present invention relates to a semiconductor element, and more particularly to the formation of a metal oxide half element with an ultra-shallow junction. Background technique [0002] As the size of transistors continues to shrink, in order to control the short channel effect, reducing the vertical junction depth and suppressing lateral diffusion of impurities have become a major challenge. The smaller the metal oxide semiconductor (hereinafter referred to as MOS) device, the greater the influence of the source / drain extension and the impurity diffusion of the heavily doped source / drain on its characteristics. In particular, when the impurities in the source / drain extension regions are significantly diffused to the channel region, problems such as short channel effect and leakage current will occur between the source and the drain. To solve the above problems, various methods have been adopted to control the diffusion of impurities. [0003] The first ...

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Problems solved by technology

However, the activation degree of arsenic is low, so the LDD sheet resistance formed by arsenic is high, thus reducing the performance of components such as the driving current of NMOS components

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