Flash controller supporting pipelined error-correcting code and configurable operations and control method thereof

Abstract

The invention is a configurable and operable flash controller supporting the pipeline error correcting code and its corresponding method, which comprises a reconfigurable control unit for controlling the whole transmission process, an internal interface unit, a flash interface unit, a check code cache and an encoding and decoding module, wherein the reconfigurable control unit are respectively communicated with the flash interface unit, encoding and decoding module, internal interface unit, and check code cache, while the encoding and decoding module is provided with the pipelined correcting algorithm module of the first, second and third levels, which can realize the pipelined decoding and error correction to the read data. By the design of the pipelined error correcting, the invention makes the data transmission and error correction conducted simultaneously, sets up the reading and writing sequence of the main data area and spare area, caches the data of spare area in the flash controller and diminishes the configuring frequency and high interaction frequency of CPU to flash controller.

Description

technical field [0001] The present invention relates to a flash controller and a control method thereof, specifically a configurable and operable flash controller and a control method thereof, the flash controller adopts an assembly line mode, which can ensure that data error correction and error detection are performed synchronously, thereby Ensure the stability and continuity of data transmission speed. Background technique [0002] Existing flash controllers mainly use 512Bytes data blocks as the basic processing unit, and perform ECC error correction at the same time. Each 512Bytes data block transmission needs to resend commands and addresses, which need to be transmitted in the current 512Bytes data blocks and ECC The transmission of a new 512Bytes data block starts only after the error correction is completed, that is, the existing solution mainly adopts a serial execution method. Figure 1 and Figure 2 respectively introduce the serial execution process. [0003] Wh...

AI Technical Summary

Problems solved by technology

[0005] In short, in the existing technical solutions: all operations are based on the 512Bytes data block as the basic operation unit, and the read and write operations are all performed in a serial manner. When some circuits of the controller are working, other Part of the circuit is in an idle state, and because each 512Bytes data block needs to perform command and address operations, as well as CPU configuration of the controller's working status and return of operation results, the existing solution requires Switching addresses requires software control, resulting in low efficiency; in data read operations, since ECC operations require more than 512 clock cycles, ECC restricts transmission performance.

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