Double-port access symmetrical dynamic memory interface

A dynamic memory and dual-port technology, applied in instruments, electrical digital data processing, computers, etc., can solve the problems that the shared memory cannot meet the read and write timing requirements of the processor, increase the waiting period of the processor, and reduce system performance.

Inactive Publication Date: 2008-06-11
TAIYUAN UNIV OF TECH
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  • Abstract
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Problems solved by technology

[0003] In order to solve the problem that under the requirements of high system performance and high-speed processors, a shared memory cannot well meet the read and write timing requirements of the processor, the processor needs to increase the waiting period, thereby reducing the overall system performance. Provides a dual-port interface to symmetric dynamic memory

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  • Double-port access symmetrical dynamic memory interface
  • Double-port access symmetrical dynamic memory interface
  • Double-port access symmetrical dynamic memory interface

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Embodiment Construction

[0023] Compared with ASIC, FPGA device has the advantages of field programming, and the mature logic implemented by FPGA can also be easily converted into ASIC. This embodiment provides a dual-port interface for accessing a symmetric dynamic memory implemented on an FPGA. In this embodiment, two pieces of DDR SDRAM of the same type are selected as the dynamic memory, and the access timing of the two processors is selected as the access timing of the asynchronous memory.

[0024] Dual ports access the interface of symmetrical dynamic memory, including central control module, processor interface module 1, processor interface module 2, dynamic memory interface module I, dynamic memory interface module II, initialization module, refresh module (as shown in Figure 1) ; In this specific implementation mode, the dynamic memory selects two DDR SDRAMs of the same model for use. Like other existing interfaces, this interface also includes a clock module, which converts the input clock ...

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Abstract

The invention relates to a computer interface, in particular to an interface of symmetrical dynamic memory with dual ports access. The invention eliminates the defects in the aspects of cost, memory capacity, system performance, usability, etc. existing in adopting dual port RAM device as a share memory and adopting time-sharing multiplexing technology of a bus to access to the share memory. The invention comprises a central control module, two processor interface modules, two memory interface modules, a refreshing module and an initialization module. The interface of the invention connects two dynamic memories with the same model and mirrored with each other as a share memory of the two processors, which realize that the two processors simultaneously access to the share memory without conflict through the interface under the requirements of high system performance and high speed processors.

Description

technical field [0001] The invention relates to a computer interface, in particular to an interface between a processor and a memory, in particular to an interface for double processor ports to access a symmetrical dynamic memory. Background technique [0002] In recent years, shared memory in multiprocessor systems is a research hotspot. Currently, there is only one access port to the shared memory, which increases the possibility of conflicts between multiprocessors accessing the shared memory. When there are two or more processors accessing the memory, only one processor is allowed to access the memory, and other processors are in a waiting state, that is, each processor cannot access the memory in parallel. In order to solve this problem, the technologies that are generally popular now mainly include: using dual-port RAM devices and time-division multiplexing technology using a bus. However, the current shared memory generally only uses one physical memory. In this way...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F3/06G06F15/167
Inventor 张刚李伟张陌谢克明
Owner TAIYUAN UNIV OF TECH
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