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A parallel realization method of SAD in motion estimation

A technology of motion estimation and implementation method, which is applied in the field of digital video codec, can solve the problems of consuming large hardware resources, the subtraction unit and the addition unit cannot be used at the same time, and cannot be completed in the same clock cycle, so as to shorten the processing time and reduce the Access, the effect of improving reuse efficiency

Inactive Publication Date: 2008-07-09
CENT ACADEME OF SVA GROUP
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Problems solved by technology

However, in this method, the subtraction unit and the addition unit cannot be used at the same time, nor can they be completed in the same clock cycle, so it does not achieve high work efficiency.
This method consumes a lot of hardware resources for high-resolution videos and large search ranges

Method used

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  • A parallel realization method of SAD in motion estimation
  • A parallel realization method of SAD in motion estimation

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Embodiment Construction

[0012] A parallel implementation method of SAD in motion estimation of the present invention will be further described in detail in conjunction with the accompanying drawings.

[0013] The present invention provides a method for parallel implementation of SAD in motion estimation, which is used for inter-frame compression processing of video coding. The method involves a plurality of processing units PE for calculating SAD, and PE calculates the pixel block of a current frame and the reference The absolute value of the pixel difference in the pixel block of the frame, and calculate the sum of the absolute difference SAD of each pixel. Please refer to Fig. 3, in the present invention, each AD unit of PE works simultaneously on the rising and falling edges of the clock, and the specific implementation process is as follows:

[0014] At time t1 (the falling edge of the clock CLK), the image frame data is input, and the reference frame data is the reference block 0 (REF0). After t...

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Abstract

The invention provides a parallel implementing method of SAD in motion estimation. The method is double-edge-triggered by a clock to parallel process addition and subtraction and ensures the SAD is carried out in single period. The method can reduce the expense of hardware resource in motion estimation by 50 percent or shorten the processing cycle in single-channel processing by 50 percent and can guarantee the real-time coding of high definition video.

Description

technical field [0001] The invention belongs to the technical field of digital video encoding and decoding, and in particular relates to a parallel implementation method of SAD in motion estimation. Background technique [0002] In existing video coding methods, most of them adopt motion estimation (MotionEstimation, ME) in units of macroblocks to realize inter-frame compression. The main function of ME is: for a coded pixel block in the current frame image, search for the pixel block with the smallest difference in a specified window in the reference frame image as the best match. There are two values ​​to be obtained in motion estimation: one is the offset of the encoded pixel block relative to the best matching pixel block in the reference frame, that is, the motion vector MV (Motion Vector); the other is the offset between the encoded pixel block and the matching pixel block SAD (Sum of Absolute Difference) of the residual absolute value. This part of the calculation a...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N7/50H04N19/139H04N19/436
Inventor 王凤麟刘锦阳
Owner CENT ACADEME OF SVA GROUP
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