A burr judgement and elimination circuit

Abstract

The present invention discloses a burr eliminating circuit which comprises a delay module which is used for detecting the width of the burr and a delay output module for eliminating the burr problem generated in specific condition. The delay module is connected with a feedback control circuit module. The delay module controls the feedback control circuit module to reset with an accelerated speed when the burr is detected and sets with an accelerated speed when the valid data is detected. The circuit of the invention totally satisfies the functions of determining and eliminating the burr and can expands the width of the valid narrow pulsewidth signal to a safe width for securing the safe operation.

Description

technical field [0001] The present invention relates to the design of analog integrated circuits in the field of microelectronics. Specifically, it is a circuit structure that uses RC delay to detect and eliminate burrs on input signals. The circuit structure can widen the effective signal with narrow pulse width to ensure its safety. Work. Background technique [0002] In chip work, the input of the signal needs to be accurate and clear. However, at present, the system application environment of many chips is poor, or due to strong external interference, at this time, the input signal of the chip will produce various types of glitches, which will seriously interfere with the integrity and correctness of the signal, and may cause the chip to malfunction. False triggering, working errors and other issues. In addition to the problems caused by regular glitches, there are also the following phenomena: [0003] Such as the clock input of ordinary circuits, if there is a glitc...

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Problems solved by technology

[0012] The above two structures have a common disadvantage, that is, in the case of continuous input of burrs with a pulse width of

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