Dynamic simulation platform method for embedded processor function verification

Abstract

The invention discloses a dynamic simulation platform method used for functional verification of an embedded processor. The method separates the control of a verification platform and the simulation flow control and respectively establishes a verification platform control center and a simulation flow control desk, the former of which is used for realizing the one-way active control flow of the verification platform and the latter is used for realizing the dynamic circulating simulation control flow, thus realizing a plurality of times of dynamic circulating operations of one-time compiling and the simulation process of the verification platform, combining the constrained random incentive generation mechanism and improving the efficiency of the functional verification. The method can provide the automated functional verification platform to the embedded processor and realize the high-efficient verification flow. The method has the advantages of high degree of automation, high verification efficiency, strong reusability, convenient maintenance and modification, etc.

Description

technical field [0001] The invention relates to the technical field of automatic function verification flow, in particular to a dynamic simulation platform method for function verification of an embedded processor. Background technique [0002] With the development of microelectronics manufacturing technology and the improvement of design process and design tools, the design scale of modern embedded processors becomes larger and larger, and the functions become more and more complex. It is difficult to meet the requirements of traditional verification methods and verification processes. Verification requirements for increasingly complex processor features and increasingly stringent time-to-market requirements. Moreover, modern embedded processors and their wide range of applications also put forward high requirements for the reliability and correctness of their design functions. The failure of embedded processor products caused by functional defects is in the incentive marke...

AI Technical Summary

Problems solved by technology

Since processor verification requires a lot of test incentives, it is very inefficient to manually write one by one, and it is easy to miss its function points

At the same time, it takes a lot of time to compile the entire functional verification platform, which also reduces the efficiency of the entire verification simulation process

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