Wall embedding type shallow groove isolation structure and method for forming same

A shallow trench isolation and oxide technology, applied in electrical components, electrical solid state devices, circuits, etc., to improve thinning problems and alleviate parasitic transistor problems

Active Publication Date: 2008-10-15
HEJIAN TECH SUZHOU
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Problems solved by technology

[0002] In the current sub-micro high-voltage process technology, shallow trench isolation technology is used for isolation between high-voltage devices, but when high-voltage devices use thicker gate oxides, in order to maintain low voltage without leakage, a fixed step height is often maintained , so that serious problems arise at the edge of the groove

Method used

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  • Wall embedding type shallow groove isolation structure and method for forming same
  • Wall embedding type shallow groove isolation structure and method for forming same
  • Wall embedding type shallow groove isolation structure and method for forming same

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Embodiment Construction

[0031] The thinned structure and formation method of the improved shallow trench isolation high voltage gate oxide in a preferred embodiment of the present invention are shown in the figure.

[0032] figure 1 represents the wafer substrate 11, figure 2 Indicates that a layer of pad oxide (PAD oxide) 12 is covered on the wafer substrate 11, image 3 It means that a layer of hard mask layer (Hardmask) 13 is deposited on the pad oxide layer 12, and the material of the hard mask layer can be silicon nitride or any other suitable material. Figure 4 expressed in image 3 In the shown structure, a layer of photoresist (Photo-Resistance) 14 is firstly coated on the surface of the pad oxide layer 12, and then the photoresist 14 at the place where the groove needs to be formed is removed, and the part where the groove needs to be formed is defined, and then the photo-resistance 14 is removed by drying. Grooves are formed by etching or wet etching, and of course other etching method...

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Abstract

The invention provides a recessed shallow slot isolation structure which comprises a substrate internally provided with a slot which is filled by a linear oxide layer and a shallow slot isolation oxide in sequence and divided into a high-pressure area and a low-pressure area, wherein, high-pressured grid oxide grows in the high-pressure area, and a slot-shaped structure is formed in the shallow slot isolation oxide at the edge of the active area where the high-pressured grid oxide grows. The invention also provides a method for forming the structure. The invention has the advantages of effectively improving the thinning problem of the high-pressured grid oxide at the upper edge of the active area, simultaneously ensuring that the low-pressure area maintains normal step height, enhancing the reliability of the high-pressure grid oxide, and relieving the parasitic transistor problem. The method can be used for the development and the application of deep submicron high-pressure advancement in the future.

Description

technical field [0001] The invention relates to a semiconductor element, in particular to a wall-embedded shallow trench isolation structure and a forming method thereof. Background technique [0002] In the current sub-micro high-voltage process technology, shallow trench isolation technology is used for isolation between high-voltage devices, but when high-voltage devices use thicker gate oxides, in order to maintain low voltage without leakage, a fixed step height is often maintained , so that serious problems arise at the edge of the groove. A new isolation structure is needed that not only improves the problem of gate oxide thinning in high-voltage devices, but also maintains normal step heights in low-voltage regions. Contents of the invention [0003] Due to the above-mentioned deficiencies of the prior art, there is an urgent need for a structure and method that does not cause thinning problems at the edges of the groove. [0004] In view of the above purpose, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/04H01L21/762
Inventor 黄清俊李召兵熊伟陈建维
Owner HEJIAN TECH SUZHOU
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