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Ciphering unit being suitable for compacting instruction set processor

A technology of encryption unit and processor, applied in the direction of public key of secure communication, machine execution device, etc., can solve problems such as cost increase

Active Publication Date: 2008-11-12
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Public key algorithms (such as RSA) and hash functions (such as SHA-1) are two major branches of cryptographic algorithms. In traditional design methods, these two algorithms are implemented separately, such as using multiple coprocessors, This will inevitably lead to an increase in cost

Method used

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  • Ciphering unit being suitable for compacting instruction set processor
  • Ciphering unit being suitable for compacting instruction set processor
  • Ciphering unit being suitable for compacting instruction set processor

Examples

Experimental program
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Embodiment Construction

[0127] The RSA / SHA multiplexing encryption unit applicable to RISC processors proposed by the present invention consists of 3 carry save adders, a carry transfer adder, 6 multiplexers, 2 32-bit registers, a 1-bit register, 5 Composed of shifters. Further describe the present invention below in conjunction with accompanying drawing.

[0128] The present invention has two working modes, RSA mode and SHA-1 mode. Mode selection is determined by the command. Such as Figure 4 As shown, the instruction memory 19 is accessed according to the address generated by the address generation unit 20, and the instruction is taken out from the instruction memory 19 and sent to the inter-stage latch 21. The instruction is decoded by the decoding unit 25 to determine which instruction it belongs to and generate The mode selection signal is sent to the RSA / SHA multiplexing encryption unit 27 after being cached by the inter-stage latch 22 for one cycle.

[0129] When the RSA / SHA multiplexing ...

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PUM

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Abstract

The invention belongs to the design technical field of integrated circuits, in particular to an encryption unit which is suitable for RISC processors, comprising a RSA encryption unit, an SHA encryption unit and a RSA / SHA reusable encryption unit. The encryption function units can be integrated into the RISC processor to accelerate the calculation of public-key algorithm and hash functions and obviously lower the cost of hardware; particularly the RSA / SHA reusable encryption unit fulfills the complex cryptography calculation through hardware, and adopts the software for finishing and configuring upper-layer RSA algorithm so as to realize the scalability of data width. The RSA / SHA reusable encryption unit being used for dealing with the most complex calculation of the cryptographic algorithm greatly accelerates the execution efficiency of the cryptographic algorithm, brings no influence on the pipeline structure of the RISC processor and increases no complexity of the hardware, thus having great compatibility with the RISC structure, and having better application prospect in information security field.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and specifically proposes an encryption unit circuit suitable for a reduced instruction set processor (RISC processor). Background technique [0002] In computer systems and communication networks, cryptographic algorithms are widely used to protect sensitive information. With the rapid development of wireless network communication technology, cryptographic computing processing capability has become an important part of the workload of many wireless devices. However, for high-density and high-intensity cryptographic operations, the relatively limited processing capability has become a bottleneck for improving the performance of handheld devices. Application-specific integrated circuit (ASIC) solutions can meet the functional and performance requirements, but lack flexibility, configurability, and scalability over the life of the device. The general-purpose processor has better flexibili...

Claims

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Application Information

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IPC IPC(8): H04L9/30G06F9/30
Inventor 韩军韩林曾晓洋
Owner FUDAN UNIV
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