Integrating analog to digital converter

An analog-to-digital converter and integration technology, applied in the field of ADC, can solve the problems affecting the output accuracy, etc., and achieve the effect of high sampling frequency, good resolution and low power consumption

Inactive Publication Date: 2008-11-12
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, process and temperature variations introduce variations in delay line operation that can affect the accuracy of the output

Method used

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  • Integrating analog to digital converter
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  • Integrating analog to digital converter

Examples

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Embodiment Construction

[0041] Fig. 1 depicts a block diagram of an ADC according to a first embodiment of the present invention. The ADC includes a DLL 2 , an integrator 4 , a comparator 6 , a digital logic circuit 8 and a sample and hold module 10 .

[0042] A reference clock source (not shown) generates a reference clock signal, which in this embodiment is a PLL but can also be implemented by other devices such as a crystal oscillator, the frequency of the reference clock signal is f s =1 / T s , where f s is the sampling frequency, T s is the sampling period. For the 180nm CMOS process, the typical sampling frequency is 250MHz, and the resolution is 7 or 8 bits. However, the speed can be increased according to technical standards. The reference clock signal is connected to the input 12 of the DLL 2 as well as to the reset input 14 of the integrator 4 and the control input of the sample and hold module 10 . The inversion of the reference clock signal is provided to the control input 16 of the ...

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PUM

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Abstract

An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number. By using a DLL to take a timing measurement, the effect of process and temperature variations is reduced by the closed loop feedback of the DLL. In another embodiment, a multiplying DLL (MDLL) is used. In a further embodiment a ring oscillator is used instead of a DLL. In that embodiment a calibration unit is used to compensate for the effects of process and temperature variations.

Description

technical field [0001] This invention relates to analog-to-digital converters (ADCs), and more particularly to ADCs that utilize timing of the integration of a signal to achieve analog-to-digital conversion. The invention also relates to a method of converting an analog signal into a digital signal. Background technique [0002] Many applications require the conversion of continuous analog signals to discrete digital signals. ADC design typically involves a tradeoff between resolution (the number of discrete levels contained in a digitized signal) and speed (the number of samples that can be sampled per second). [0003] Integrating ADC is known. They can achieve high resolution by timing the integration of the signal to a reference level. The time taken is proportional to the amplitude of the signal to be converted into a digital signal. Integrating ADCs require a high precision timing reference that can operate at frequencies many times higher than the sampling frequen...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/50
CPCH03M1/52
Inventor 弗里德尔·格费斯沃尔夫冈·菲尔特纳
Owner NXP BV
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