Multi-layer high quality gate dielectric for low-temperature poly-silicon tfts

Abstract

A method and apparatus that is useful for forming a high quality gate dielectric layer in MOS TFT devices using a high density plasma oxidation (HDPO) process. In one embodiment a HDPO process layer is formed over the channel, source and drain regions to form a dielectric interface and then one or more dielectric layers are deposited on the HDPO layer to form a high quality gate dielectric layer. The HDPO process generally uses an inductively and / or capacitively coupled RF transmitting device to generate and control the plasma generated over the substrate and injecting a gas containing an oxidizing source to grow the interfacial layer. A second dielectric layer may then be deposited on the substrate using a CVD or PECVD deposition process. Aspects of the invention also provide a cluster tool that contains at least one specialized plasma processing chamber that is capable of depositing a high quality gate dielectric layer.

Description

technical field [0001] Embodiments of the present invention relate to an apparatus and method for manufacturing electronic components using a plasma processing system. Background technique [0002] Metal interconnects and other features are formed by depositing and removing layers of conductive, semiconducting, and dielectric materials on glass substrates in the fabrication of flat panel displays (FPDs), thin film transistors (TFTs), and liquid crystal cells. The resulting various features are integrated in a system to produce an active matrix display screen in which the display state is generated in each pixel on the FPD. The manufacturing process technologies used to produce FPDs include plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), etching, and the like. Plasma processing is particularly suitable for the production of flat panel displays because it requires relatively low manufacturing process temperatures during the deposition of th...

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Problems solved by technology

Since the high-temperature deposition process will cause the dopant to diffuse inside the deposited film layer, the high-temperature deposition process (for example, higher than 600°C) cannot be used to form a good interface between the deposited film layer and the p-Si channel layer. And it may not be suitable for glass substrates with thin films deposited on it because the glass may become soft and cause dimensional instability

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