Chip stack packaging structure and method of producing the same

Abstract

The invention provides a chip stack packaging structure and a manufacturing method thereof, the packaging structure comprises: a substrate, a first chip, a circuit substrate and a second chip, wherein, the substrate is provided with a first surface and an opposite second surface, the first chip is positioned at the first surface of the substrate, provided with a first driving surface and an opposite first wafer backside, and electrically connected with the substrate by the flip chip packaging bonding mode. The circuit substrate is formed on the first wafer backside, comprising a dielectric layer which is arranged on the first wafer backside and a patterned circuit layer which is formed on the dielectric layer, and the patterned circuit layer is electrically connected with the substrate by a wire bond. The second chip is positioned on the patterned circuit layer, comprising a second driving surface and at least one second welding pad which is arranged on the second driving surface, wherein, the welding pad is electrically connected with the patterned circuit layer and further electrically connected with the substrate by the wire bond.

Description

technical field [0001] The present invention relates to a semiconductor package structure, and more particularly, to a stack package structure and a manufacturing method thereof. Background technique [0002] With the rapid increase in the demand for electronic product functions and applications, packaging technology is also developing in the direction of high-density miniaturization, single-chip packaging to multi-chip packaging, and two-dimensional to three-dimensional scales. Among them, SystemIn Package is a better method for integrating chips with different circuit functions. Surface Mount Technology (SMT) technology is used to integrate different chip stacks on the same substrate, thereby effectively reducing the packaging area. It has the advantages of small size, high frequency, high speed, short production cycle and low cost. [0003] Please refer to FIG. 4 . FIG. 4 is a structural cross-sectional view according to a conventional chip stack package structure 400 . ...

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a chip stack packaging structure package to solve the problems in the prior art that the length of the wiring that electrically connects the upper chip and the substrate is too long and the wire arc is too large, so as to solve the current problem. The problem of low yield sealing and low packaging density of technical chip stack packaging structure

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