Check patentability & draft patents in minutes with Patsnap Eureka AI!

Method for preparing thin-film transistor array substrate

A technology for thin film transistors and array substrates, which is applied in the field of manufacturing thin film transistor array substrates, can solve problems such as by-products, poor uniformity, and rough surface of a protective layer, thereby simplifying production processes, reducing process complexity and process costs, The effect of improving process yield

Active Publication Date: 2008-12-24
AU OPTRONICS CORP
View PDF0 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The invention provides a method for manufacturing a thin film transistor, which can improve the problems of rough surface of the protective layer, poor uniformity, or by-products produced in the process.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for preparing thin-film transistor array substrate
  • Method for preparing thin-film transistor array substrate
  • Method for preparing thin-film transistor array substrate

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0075] 3A to 3H are schematic diagrams of the manufacturing process of the thin film transistor array substrate according to the first embodiment of the present invention. Referring to FIG. 3A , firstly, a substrate 310 having a plurality of pixel regions 310A arranged in an array and peripheral circuit regions 310B is provided. For convenience of description, only one pixel region 310A is shown in the figure for representative illustration. The material of the substrate 310 is, for example, a transparent substrate such as glass, quartz or plastic. Next, gate patterns 320 are respectively formed on the substrate 310 in each pixel area 310A, and a plurality of first pad patterns 322 are formed on the substrate 310 in the peripheral line area 310B, so that the gate patterns 320 and the first pad patterns are formed. The method of the pad pattern 322 can be, for example, firstly forming a first metal layer (not shown) on the substrate 310, and then patterning the first metal laye...

no. 2 example

[0087] 4A and 4H further illustrate the manufacturing process of another thin film transistor array substrate according to the second embodiment of the present invention. To simplify the description, this embodiment will not describe the parts similar to the manufacturing process shown in FIGS. 3A-3H . As shown in FIG. 4F , compared with the first embodiment, the drain pattern 360D or the source pattern 360S of this embodiment does not extend above the electrode pattern 324 . Next, as shown in FIG. 4G , the patterned passivation layer 370 further has a fourth opening H4 in each pixel region 310A to expose the gate insulating layer 330 above the corresponding electrode pattern 324 . After that, as shown in FIG. 4H , after forming the pixel electrode 380 and the third pad pattern 382, ​​each pixel electrode 380 is further connected to the gate insulating layer 330 exposed by the fourth opening H4 through the corresponding fourth opening H4. , so that the electrode pattern 324 ,...

no. 3 example

[0090] 5A to 5H are schematic diagrams of the manufacturing process of the thin film transistor array substrate according to the third embodiment of the present invention. FIG. 5A is similar to that shown in FIG. 3A , but the first electrode pattern 324 in this embodiment is equivalent to the electrode pattern 324 in the first embodiment. As shown in FIG. 5B , compared with the first embodiment, in this embodiment, after the gate insulating layer 330 and the semiconductor layer 340 are formed, a metal layer 360 is formed on the substrate 310 together, and the metal layer 360 covers each pixel area. 310A and the peripheral circuit region 310B include a cover gate pattern 320 and a first pad pattern 322 , wherein the semiconductor layer 340 includes a channel layer 342 and an ohmic contact layer 344 on the channel layer 342 .

[0091]Next, please continue to refer to FIG. 5B, a patterned photoresist layer 350 is formed on the metal layer 360, wherein the patterned photoresist la...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a manufacturing method of a film transistor array substrate, which comprises the following steps: first, a gate pattern and a first pad pattern are respectively formed on the substrate, a gate insulated layer and a semiconductor layer are formed in sequence to cover the two patterns. Then a patterned photoresist layer is formed and the photoresist block thickness and the proper patterns of the patterned photoresist layer in different regions are adjusted. The semiconductor layer and the gate insulated layer over the first pad pattern are removed by an etching process and reducing patterned photoresist layer process. Furthermore, the patterned photoresist layer is removed to form a source pattern, a drain pattern and a second pad pattern which is electrically connected with the first pad pattern. Later, a patterned protective layer is formed on the patterned photoresist layer, and the patterned protective layer is provided with a second open which exposes the source pattern or the drain pattern and a third open which exposes the second pad pattern.

Description

technical field [0001] The present invention relates to a manufacturing method of an array substrate, and in particular to a manufacturing method of a thin film transistor array substrate. Background technique [0002] Generally speaking, a thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate, a liquid crystal layer and a backlight module. [0003] FIG. 1A to FIG. 1F are flowcharts of a conventional thin film transistor array substrate, and only a group of pixels and pads are shown in the figures for illustration. As shown in FIG. 1A , firstly, a substrate 10 is provided, and a gate pattern 20 , a first pad pattern 22 and a first electrode pattern 24 are formed on the substrate 10 through a first masking process. Next, a gate insulating layer 30 and a semiconductor layer (not shown) are continuously deposited on the substrate 10 to cover the gate pattern 20 , the first pad pattern 22 and the...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/84
Inventor 曾贤楷林汉涂詹勋昌方国龙
Owner AU OPTRONICS CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com