Flash memory and manufacturing method thereof

Abstract

A flash memory includes a substrate, a stack structure located on the substrate, a source electrode and a drain electrode, and a source terminal spacer layer, wherein the stack structure includes a tunnel oxide layer, a charge storage layer located on the tunnel oxide layer, and a charge storage layer located on the tunnel oxide layer. an inter-gate dielectric layer on the storage layer and a control gate located on the inter-gate dielectric layer. The source electrode and drain electrode are located in the substrate on both sides of the charge storage layer. The source end spacer layer is located on the side wall of the stack structure close to the source to prevent the tunnel oxide layer and the inter-gate dielectric layer from being re-oxidized near the source end and causing an increase in thickness.

Description

technical field [0001] The present invention relates to a non-volatile memory and its manufacturing method, and in particular to a flash memory with an asymmetric spacer layer structure and its manufacturing method. Background technique [0002] A typical flash memory uses doped polysilicon to make a charge storage layer and a control gate. When the memory is being programmed, appropriate programming voltages are applied to the source, drain and control gate respectively, and electrons will flow from the source to the drain through a channel. During this process, some electrons will pass through the tunneling oxide layer under the polysilicon charge storage layer, enter and be evenly distributed in the entire polysilicon charge storage layer, such electrons pass through the tunneling oxide layer The phenomenon of entering the polysilicon charge storage layer is called tunneling effect. The tunneling effect can be divided into two cases, one is called channel hot-electron i...

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Problems solved by technology

[0006] However, if Figure 1B As shown, after the annealing process 116, whether it is the edge thickness t of the tunnel oxide layer 102 or the inter-gate dielectric layer 106 edge both become thicker than their central thickness t center Thick, so it is not conducive to the control of the gate coupling ratio (gate coupling ratio, GCR) between the charge storage layer and the control gate, which affects the operating voltage and device speed

Moreover, when the flash memory performs an erase operation, the area between the tunnel oxide layer 102 and the channel (that is, the area between the source electrode 118a and the drain electrode 118b) is related, so when the edge of the tunnel oxide layer 102 When thickened, it will not be conducive to the erasing operation of the component

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