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Packaging structure, packaging method and photosensitive device

A technology of packaging structure and packaging method, which is applied in the direction of radiation control devices, electrical components, electric solid devices, etc., can solve the problem of reducing the available area of ​​the wafer, and achieve the effect of reducing the thickness

Active Publication Date: 2009-02-18
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Furthermore, in the prior art, it may also be necessary to set an extended pad (not shown) in addition to the pad 115 on the chip 120, so that the available area of ​​the wafer for manufacturing the chip 120 is reduced.

Method used

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  • Packaging structure, packaging method and photosensitive device
  • Packaging structure, packaging method and photosensitive device
  • Packaging structure, packaging method and photosensitive device

Examples

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Embodiment Construction

[0019] The present embodiment provides a package structure and a corresponding package method, which avoids the need to form a multi-layer cladding structure when bumps are formed on the chip side of the package structure in the prior art, thereby effectively reducing the thickness of the package structure.

[0020] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings, taking the packaging of the optical sensor chip as an example.

[0021] A schematic structural diagram of an embodiment of the packaging structure in this application is as follows image 3 As shown, the package structure 200 includes a substrate 205 , a chip 220 pressed against the substrate 205 , and solder bumps 250 , and the solder bumps 250 are disposed on the substrate 205 . In order to facilitate the contact between the solder bumps 250 and the printed circuit board during the subsequent assembly process of the package structure ...

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Abstract

The invention provides a package structure, package method and a sensitization device. The package structure includes a substrate, chips and welding spots for the electrical connection with weld pads on the chip. The welding spots are disposed on the substrate, which can avoid that the prior art form a multi-layer cover structure as forming the spots on one side of the chip of the package structure thereby reducing thickness of the package structure and enhancing the reliability of the package structure.

Description

technical field [0001] The present application relates to a package structure, a package method for forming the package structure, and a photosensitive device formed from the package structure. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology of packaging and testing a whole wafer and then cutting to obtain a single finished chip, and the size of the packaged chip is the same as that of the bare chip. Wafer-level chip size packaging technology has changed the traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier) and digital camera module model, in line with the market for microelectronics products Increasingly light, small, short, thin and low-cost requirements. The chip size packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the chip cost is significantly reduced with t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L27/146H01L21/60
CPCH01L2924/14H01L27/14636H01L27/14627H01L31/0203H01L27/14685H01L27/14618H01L2924/01079H01L24/16H01L2924/3025H01L31/0232H01L27/14683H01L2224/05569H01L2224/05008H01L2224/05548H01L2224/05001H01L2224/05624H01L2224/05644H01L2224/05655H01L2924/00014H01L24/13H01L24/05H01L2224/02377H01L2224/02371H01L2224/131H01L2224/13024H01L2224/05099H01L2924/01028H01L2924/014
Inventor 王之奇俞国庆邹秋红王蔚
Owner CHINA WAFER LEVEL CSP