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Semiconductor device and method for fabricating same

A semiconductor and device technology, applied in the field of semiconductor devices and their manufacturing, can solve the problems of reducing the yield and increasing the defect density of the first gate insulating film, etc.

Inactive Publication Date: 2009-02-25
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, a bird's beak is formed on the substrate at the end of the gate by thermal oxidation, thereby increasing the defect density of the first gate insulating film near the end of the gate, lowering the yield

Method used

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  • Semiconductor device and method for fabricating same
  • Semiconductor device and method for fabricating same
  • Semiconductor device and method for fabricating same

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0038] Figure 14is a top view of Example 1 of the present invention. Figure 15 (a) and 15(b) are along Figure 14 The cross-sectional view extracted by lines A-A and B-B. exist Figure 14 and 15 in, with Figure 9 and 10 The same parts as those in the first exemplary embodiment shown in the Figure 9 and 10 The same reference numerals are denoted in and repeated explanations thereof are omitted. In this example, the portion of the charge accumulating layer 4 immediately below the gate conductor 6 becomes the high trap surface density region 4a, and a part of the outer portion of the gate conductor becomes the trap surface density lower than that of the high trap surface density region 4a. The low trap surface density region 4b, and the part outside of this part becomes the non-trap region 4c that does not contain charge traps. The non-trap region 4c contains no nitrogen and is almost completely converted into a silicon oxide film. In the memory cell of Example 1, e...

example 2

[0040] Figure 16 is a top view of Example 2 of the present invention. Figure 17 (a) and 17(b) are along Figure 16 The cross-sectional view extracted by lines A-A and B-B. exist Figure 16 and 17 in, with Figure 9 and 10 The same parts as those in the first exemplary embodiment shown in the Figure 9 and 10 The same reference numerals are denoted in and repeated explanations thereof are omitted. In this example, the portion of charge accumulating layer 4 immediately below gate conductor 6 becomes high trap surface density region 4a, and the portion outside the end of the gate conductor becomes non-trap region 4c free of charge traps. The non-trap region 4c outside the end of the gate conductor does not contain nitrogen and is almost completely converted into a silicon oxide film. In the memory cell of Example 2, there were no charge traps at the portion outside the gate conductor. The charge accumulation layer 4 inside the gate conductor 6 or inside the gate condu...

example 3

[0042] Figure 18 is a top view of Example 3 of the present invention. Figure 19 (a) and 19(b) are along Figure 18 The cross-sectional view extracted by lines A-A and B-B. exist Figure 18 and 19 in, with Figure 9 and 10 The same parts as those in the first exemplary embodiment shown in the Figure 9 and 10 The same reference numerals are denoted in and repeated explanations thereof are omitted. In this example, the portion of the charge accumulation layer 4 immediately below the gate conductor 6 becomes the initial film thickness region 4d whose thickness remains unchanged, but the region of the charge accumulation layer 4 outside the gate conductor becomes the thickness region 4d. Thin film region 4e smaller than initial thickness. A portion of the charge accumulating layer 4 becomes a non-trap region 4c. In this example, the charge accumulating layer (4e) including the charge traps outside the end of the gate electrode is made thinner than the charge accumulati...

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Abstract

A trap type memory element in which inflow of charges into a charge storage region from the outside, external diffusion of stored charges and outflow caused by a defect are suppressed. A gate conductor (6) is formed on a silicon substrate (1) through a multilayer insulating film consisting of a first gate insulating film (3), a charge storage layer (4), and a second gate insulating film (5). The multilayer insulating film (3-5) is projecting to the outside of the gate conductor (6) and extending below the outer end of a sidewall (8). The charge storage layer (4) has a high trap surface density region (4a) directly under the gate conductor, and a low trap surface density region (4b) on the outside of the gate conductor.

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, to a semiconductor device including a rewritable nonvolatile semiconductor memory represented by a flash memory and a manufacturing method thereof. Background technique [0002] LSI including flash memory continues to be miniaturized, and has entered the 65nm era from the current 0.13μm and 90nm node era. Therefore, although flash memory mainly used floating gate (FG) memory cells until the era of the 0.13 μm node in order to meet the requirements for reducing the cell area and thinning the insulating film, since it has been found that in the era of the 90nm node or later Since it is difficult to thin the insulating film to ensure the retention property, attention has been paid to a trap memory that traps charges using traps discretely included in the insulating film. Compared with the FG memory, the trap memory has the advantages of reducing...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H01L29/788H01L29/792
CPCG11C16/0466H01L29/4234H01L29/66833H01L21/28282H01L27/115H01L29/792H01L27/11568H01L29/40117H10B69/00H10B43/30
Inventor 寺井真之
Owner NEC CORP
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