Interconnection structure
An interconnect structure, copper metal technology, applied in electrical components, electrical solid devices, circuits, etc., can solve problems such as occupation, multi-semiconductor chip surface area, etc.
Inactive Publication Date: 2009-03-04
MEDIATEK INC
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Problems solved by technology
[0008] In order to solve the above-mentioned problem that the top metal layer occupies more surface area of the semiconductor chip, the present invention provides an interconnection structure to improve the connection between the RDL and the highest copper metal layer, thereby reducing the surface area of the semiconductor chip occupied by the highest copper metal layer
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[0014] The present invention relates to a single connection structure between a re-distribution layer (RDL) and the highest copper metal layer.
[0015] see image 3 . image 3 It is a schematic cross-sectional view of the upper part of the semiconductor chip 10 according to an embodiment of the present invention. The semiconductor chip 10 includes a topmost copper metal layer 12 embedded in an inter-layer dielectric 13 . The highest copper metal layer 12 is formed by conventional copper damascene method and can be used as a power layer.
[0016] Those skilled in the art know that the copper damascene method provides a solution for forming conductive wires coupled to integral via plugs without dry etching copper. Single damascene or dual damascene structures can be used to connect devices and / or wires of integrated circuits.
[0017] Generally speaking, the dual damascene process includes trench-first process, via-first process, partial-via-first process and self-aligned ...
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Abstract
The present invention provides an interconnection structure which comprises an inner dielectric layer, a topmost copper metal layer, an insulating layer, a via opening and a redistributing layer. The topmost copper metal layer is inlaid in the inner dielectric layer. The insulating layer is above the inner dielectric layer and the topmost copper metal layer. The via opening is in the insulating layer and is used for exposing the upper surface of the topmost copper metal layer, wherein the via opening comprises an upper conducting part and a lower conducting part. The upper conducting part diminishes gradually inwards and the lower conducting part has an external shape of approximate vertical well wall. The redistributing layer comprises an aluminum layer filling to the via opening. The interconnection structure can reduce the surface area of semiconductor chip taken by the topmost metal layer. The step coverage percentage is improved and the reliability of chip is increased simultaneously.
Description
technical field [0001] The present invention relates to semiconductor devices, in particular to a metal interconnection structure of a semiconductor chip, which can improve the layout source of the semiconductor chip on the highest copper metal layer. Background technique [0002] Reducing the process size of a semiconductor device through the prior art semiconductor technology greatly improves the device packing density of a single integrated circuit (Integrated Circuit, IC) chip. However, as device storage density increases, the number of electrical metal interconnection layers on an IC chip must be increased while reducing chip size to efficiently wire up power to different devices on the substrate. For example, it is common in the art to have two to six metal interconnect layers in a single IC chip. [0003] figure 1 is a schematic cross-sectional view of the upper part of a semiconductor chip 1 according to the prior art. The semiconductor chip 1 includes a top metal...
Claims
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IPC IPC(8): H01L23/522
CPCH01L23/53214H01L2924/0002H01L23/53238H01L23/525H01L2924/00
Inventor 杨明宗张添昌
Owner MEDIATEK INC