Field effect transistor construction adopting heavy doped conduction substrate, inverse groove and earthed source pole

A field effect transistor, heavily doped technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of larger package size, larger device size, and increased device cost.

Active Publication Date: 2009-03-18
ALPHA & OMEGA SEMICON LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The large cell pitch causes the device size to become larger, and the p

Method used

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  • Field effect transistor construction adopting heavy doped conduction substrate, inverse groove and earthed source pole
  • Field effect transistor construction adopting heavy doped conduction substrate, inverse groove and earthed source pole
  • Field effect transistor construction adopting heavy doped conduction substrate, inverse groove and earthed source pole

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[0023] Refer to figure 2 A cross-sectional view of an inverted trench FET device of the present invention with bottom source and top drain (ie, the source is at the bottom and the drain is at the top) and the source of the N-channel is grounded. The N-channel reverse-groove FET device whose source is grounded is supported on a P+ substrate 105 that functions as a bottom source. The alternative is to form P-channel devices on an N+ Si substrate, or use silicon carbide, gallium nitride (GaN) or other semiconductor substrates. A P epitaxial growth layer 110 is formed on top of the substrate 105. The active unit area is arranged on the substrate, and the termination area is usually arranged on the periphery of the substrate. The FET device 100 has a plurality of trenches opening on the top surface of the substrate, which are as deep as the lower part of the epitaxial growth layer 110. The trench opened in the active cell area is wider to form a gate. The sidewall of the trench to whic...

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Abstract

The invention discloses a field-effect transistor (MOSFET) which adopts a conduction base of a heavy base, a reverse groove and a grounding source electrode, wherein a trench gate composed by the transistor is surrounded by a source electrode region and a body region below a drain region, and a source electrode is arranged on the bottom surface of the base. The MOSFET further comprises a shaded gate trench (SGT) structure which is arranged on the lower portion of the trench gate, and is insulated with the trench gate. The SGT actually forms a round hole whose transverse stretching degree exceeds the trench gate, and is covered by a layering of dielectric, which is filled with trench gate material. The round hole is formed by isotropic etching on the bottom of the trench gate, and is insulated with the trench gate by an oxide insulating layer. The transverse stretching degree of the round hole exceeds the trench walls, thereby playing the role of vertically arranging guide posts to control the depth of the trench gate. The decrease of the capacitor (Cgd) from the gate of the MOSFET to the drain depends on the controllable depth of the trench gate.

Description

technical field [0001] The present invention relates to a semiconductor power device, in particular to a reverse trench and source grounded field effect transistor (FET) structure comprising a conductive substrate using a heavily doped P+ substrate. Background technique [0002] For semiconductor power devices including FETs, metal oxide semiconductor field effect transistors (MOSFETs) and junction field effect transistors (JFETs) that contain source inductance, conventional technologies face some technical difficulties and limitations in further reducing their source inductance. In particular, those skilled in the art face technical challenges to reduce the source inductance. At the same time, since more and more power device applications require these devices to have high efficiency, high gain, and high-frequency capabilities, these growing demands for semiconductor power devices require reducing their source inductance. In general, source inductance can be reduced by eli...

Claims

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Application Information

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IPC IPC(8): H01L29/78
Inventor 弗兰克斯·赫尔伯特
Owner ALPHA & OMEGA SEMICON LTD
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