Double data rate interface

Abstract

The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Description

technical field [0001] The present invention relates to double data rate (DDR) synchronous dynamic random access memory (SDRAM), and in particular to interface timing systems, and delay locked loops for use therein. Background technique [0002] As we all know, SDRAM uses a square wave clock signal to transfer data. Like most synchronous circuits, traditional SDRAM architectures perform data transfers on clock low-to-high transitions and ignore the opposite high-to-low transition. DDR-SDRAM, on the other hand, operates on both low-to-high and high-to-low transitions, thereby doubling the transfer rate for a particular clock rate, or on the other hand, converting the The clock rate is halved. [0003] Figure 1a shows the main elements of the interface employed in DDR transmission, while Figure 1b shows a typical timing diagram for such a transmission. The clock signal CLK is sent from the processor to the DDR memory. DDR memory uses this signal to generate "read" cycle c...

AI Technical Summary

Problems solved by technology

[0015]The timing delay issues discussed above are common to high speed DDR interfaces and can come from various sources such as memory chips not meeting JEDEC specifications, or by The timing delay introduced by the printed circuit board of the memory chip

Also, it should be realized that the problem of timing delay will grow with the increase of clock frequency

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