High dielectric constant grid dielectric material forming method and a semiconductor device

Abstract

This invention provides a method for forming grid dielectric material with high permittivity and a semiconductor component. The method comprises following steps: providing a semiconductor substrate; cleaning the substrate; performing a thermal treatment; performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer. The method of this invention can generate a uniform and thin interface layer having proper tail end so as to make it be compatible with the subsequent deposition of the high-k dielectric material deposition, and it can improve the roughness and the quality of the interface layer. At the same time, the structure of this invention can improve the electric load current carrier migration rate in the semiconductor component.

Description

technical field [0001] The present invention relates to a method for preparing an integrated circuit, and more particularly to a method for depositing a high dielectric constant material on a substrate, thereby providing an interface layer suitable for the deposition of the high dielectric constant material, and also relates to preparing a gate dielectric structure method for depositing high dielectric constant materials. Background technique [0002] There is currently a need to shrink (reduce) the size of semiconductor components to increase component density over semiconductor chips so that the semiconductor components operate faster and consume less power. [0003] Silicon dioxide is most commonly used as the gate dielectric material for semiconductor components. However, when silicon dioxide is used as a gate dielectric material, as the silicon dioxide thickness decreases, there is an accompanying severe restriction on the oxidation process. When using these dielectri...

AI Technical Summary

Problems solved by technology

[0012]The challenge here is to optimize the quality of the interfacial layer between the semiconductor wafer substrate (especially a silicon dioxide wafer substrate) and the high dielectric constant material Because the quality here will determine the performance and reliability of the final transistor

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