Unlock instant, AI-driven research and patent intelligence for your innovation.

NOT gate logic circuit and its forming method

A technology of logic circuits and NOT gates, applied in logic circuits, logic circuits with logic functions, circuits, etc., and can solve problems such as restricting the application of logic circuits

Active Publication Date: 2009-05-13
SOI MICRO CO LTD
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since intrinsic ZnO is an N-type semiconductor, and most of the fabricated ZnO NW FETs are depletion-type devices, the application of ZnO nanowire materials to realize logic circuits based on enhancement / depletion-type FETs is restricted.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • NOT gate logic circuit and its forming method
  • NOT gate logic circuit and its forming method
  • NOT gate logic circuit and its forming method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] figure 1 It is a schematic diagram of the structure of a NOT logic circuit of the present invention. The NOT logic circuit includes an input terminal for receiving an input voltage signal Vin; an enhanced back-gate ZnO NW FET 100, the gate electrode G1 of which is coupled to the input terminal, and the source electrode S1 of which is coupled to the ground point; and A depletion type back gate ZnONW FET 200, the drain electrode D2 of which is coupled to the voltage source ( figure 1 The medium voltage source is a DC power supply V DD ), the gate electrode G2, the source electrode S2, and the drain electrode D1 of the enhanced back-gate ZnO NW FET 100 are coupled to a point A, and the point A is used as an output terminal for outputting a voltage signal Vout.

[0020] Since the gate electrode G2 of the depletion type back gate ZnO NW FET 200 is connected to the source electrode S2, the gate voltage of the depletion type back gate ZnO NW FET 200 is zero volts, which is grea...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a 'NOT' logic circuit and a fabricating method thereof. The 'NOT' logic circuit comprises an input terminal, an enhancement type back-gate ZnO nanowire field effect transistor, and a depletion mode back-gate ZnO nanowire field effect transistor. The input terminal is used for receiving an input voltage signal; the gate electrode of the enhancement type back-gate ZnO nanowire field effect transistor is connected to the input terminal, and the source electrode thereof is coupled to an earth point; the drain electrode of the depletion mode back-gate ZnO nanowire field effect transistor is coupled to a voltage source, and the gate electrode and the source electrode of the depletion mode back-gate ZnO nanowire field effect transistor, and the drain electrode of the enhancement type back-gate ZnO nanowire field effect transistor are coupled at a point; and the point serves as an output terminal used for outputting the voltage signal. The invention utilizes the manufacturing technology and the interconnection technology of ZnO nanowire materials and ZnO nanowire field effect transistors, and fabricates the 'NOT' logic circuit based on the direct coupling field effect logic of the ZnO nanowire field effect transistor.

Description

Technical field [0001] The present invention relates to the field of compound semiconductor materials and devices, in particular to a direct-coupled FET Logic (DCFL) NOT logic circuit based on a back-gate zinc oxide nanowire field effect transistor and a method for forming the same. Background technique [0002] ZnO is a new type of multifunctional compound semiconductor material with direct band gap of II-VI group, which is called the third-generation wide-gap semiconductor material. The ZnO crystal has a wurtzite structure, the forbidden band width is about 3.37 eV, and the exciton binding energy is about 60 meV. ZnO has the characteristics of semiconductor, photoelectric, piezoelectric, pyroelectric, gas sensitivity and transparent conductivity, and has broad potential application value in many fields such as sensing, sound, light, and electricity. [0003] In recent years, research on ZnO materials and devices has received extensive attention. The research scope covers the gr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20H03K19/094H01L27/02H01L27/088H01L29/78H01L21/336
Inventor 徐静波张海英
Owner SOI MICRO CO LTD