Low power consumption parallel wavelet transforming VLSI structure

A technology of wavelet transform and discrete wavelet transform, applied in the field of VLSI structure of wavelet transform, can solve the problems of increasing chip area and control complexity, and achieve the effect of improving data throughput, reducing access, and reducing power consumption

Inactive Publication Date: 2009-09-16
INST OF ACOUSTICS CHINESE ACAD OF SCI
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  • Description
  • Claims
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Problems solved by technology

However, the additional row buffer increases the chip area and the complexity of control

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  • Low power consumption parallel wavelet transforming VLSI structure
  • Low power consumption parallel wavelet transforming VLSI structure
  • Low power consumption parallel wavelet transforming VLSI structure

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Embodiment Construction

[0024] The following takes the realization of (9 / 7) wavelet as an example to introduce the specific implementation of the present invention.

[0025] Such as figure 1 As shown, when the lifting algorithm is directly implemented, the incoming signal is firstly split by parity, and then each group of numbers (an even sequence number and an odd sequence number) enters the subsequent lifting implementation steps at intervals of one cycle. Therefore, the entire data path is idle for nearly half of the time, and the processing speed and efficiency are not high.

[0026] Such as figure 2 As shown, the low-power parallel one-dimensional discrete wavelet transform VLSI structure proposed by the present invention, in the directly realized one-dimensional discrete wavelet transform VLSI structure, before each adder of the data stream, two parallel connected Delay unit / shift register and a data stream selector; the selx signal selects a data stream path from the two data stream paths every ...

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Abstract

The invention relates to a low power consumption parallel wavelet transforming VLSI structure, wherein the low power consumption parallel wavelet transforming VLSI structure is connected with two parallel delay cells and a data stream selector or two shunt-wound shift registers and a data stream selector in series before each adder of the data stream in a VLSI structure which directly realizes discrete wavelet transformation; an embedded boundary extension circuit is parallelly and synchronously connected with a structure in which two shunt-wound delay cells/shift registers and a data stream selector form a group. The invention can process two lines of data synchronously to realize time sharing multiplex of main arithmetic units with the hardware utilization rate up to 100%, and reduce the required cache on chips and the access to the exterior memory, thereby efficiently decreasing the power consumption of the whole design. Due to the simple hardware structure, the VLSI is easy to realize.

Description

Technical field [0001] The present invention relates to the technical field of VLSI design, a hardware realization structure of discrete wavelet transform in video and image coding standards, in particular to a low-power parallel wavelet transform VLSI structure. Background technique [0002] In recent years, with the rapid development of computer and digital communication technology, especially the rise of network and multimedia technology, image coding and compression technology has received more and more attention. At the same time, under the limitation of communication bandwidth and storage capacity, it is very important to encode and compress images. Wavelet transform has good time-frequency characteristics, overcomes the shortcomings of traditional DCT coding that will produce block effects at low bit rates, and can flexibly implement multiple functions. Therefore, it has been widely used in the field of static and dynamic image compression. It has become the core transform...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N7/30G06T9/00G06F17/14H04N19/436H04N19/63
Inventor 刘鸿瑾王东辉张铁军侯朝焕
Owner INST OF ACOUSTICS CHINESE ACAD OF SCI
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