Fin grids transistor surrounded with grid electrodes and manufacturing method thereof

Abstract

A fin grids transistor surrounded with grid electrodes comprises a substrate, an insulating layer, a semiconductor layer, a grid medium layer, a control grid, a source electrode region and a drain electrode region; wherein the insulating layer and the semiconductor layer are arranged on the surface of the substrate in turn, the surface of the insulating layer close to the semiconductor layer is provided with a pit, and the semiconductor layer comprises a suspended part over the pit; the grid medium layer surrounds the suspended part of the semiconductor layer over the pit; and the control grid is arranged on the surface of the insulating layer and comprises a part surrounding the grid medium layer. The transistor and the manufacturing method have the advantages of improving the control capability of the grid electrode to conductive channels and the electric performance of the transistor, and have the advantages of high integration degree, low cost, and the like.

Description

【Technical field】 [0001] The invention relates to the field of semiconductor devices, in particular to a surrounding gate fin-gate transistor device and a manufacturing method thereof. 【Background technique】 [0002] In the past few decades, each improvement in the performance of silicon-based CMOS devices is mainly brought about by the reduction of device size, mainly including the reduction of channel length, gate oxide thickness and threshold voltage. However, the feature size of integrated circuits began to shrink to sub-100 nanometers in 1999, and entered the era of nanotechnology. Problems such as the physical basis of traditional devices. Especially starting from the 90nm node, because the gate oxide leakage current increases sharply when the gate oxide thickness is below the critical thickness, the scaling down of the traditional gate oxide thickness has reached its limit. Therefore, we must seek breakthroughs in basic research fields such as device physics, materi...

AI Technical Summary

Problems solved by technology

However, conventional FinFETs are prepared on (100) substrates, which has limited performance improvement for pFETs, and conventional FinFETs only control the channel from both sides, and the control capability is limited.

In addition, traditional FinFET devices are distributed in a two-dimensional direction, that is, nFETs and pFETs are prepared separately, which limits the further improvement of device integration

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