[0057] Example one
[0058] The portable power communication protocol detector of this embodiment is such as figure 1 with figure 2 As shown, it includes a collection device 1 and an analysis device 2 arranged in a handheld case. The acquisition device 1 contains a message listener and a parallel-to-serial processor; among them, the message listener is mirrored by the switch port, the signal message listener 4, the network signal message listener 5, and the serial signal message listener. The listener 6 and the MODEM carrier signal message listener 7 are composed of four message listeners, and the parallel-to-serial processor is composed of FPGA processor 3. The analysis device includes a CPU8, an analysis system 11, an input 9 and a display 10 respectively connected to the CPU8; among them, the CPU8 uses an embedded processor (model is MPC8377), and the input 9 uses a keyboard, mouse or touch screen input device, etc., the display 10Using general-purpose CRT or liquid crystal display. The respective input ends of the above four message listeners are respectively connected to the switch communication link 13, the network communication link 14, the serial power communication link 15 and the carrier power communication link 16. The four message listeners are Each output terminal is connected to the input terminal of FPGA processor 3 in parallel. The output end of the FPGA processor 3 is serially connected to the CPU 8 through a gigabit network port, and the respective control ends of the aforementioned four message listeners and the FPGA processor 3 are respectively connected to the CPU 8.
[0059] Since the output ends of the above four message listeners are respectively connected to the input end of FPGA processor 3 in parallel, the output rate of the four message listeners is generally 10M or 100M, and the Gigabit network of FPGA processor 3 The output rate of the port is much higher than the input rate from the four message listeners, and the messages transmitted by the four message listeners are output after the FPGA processor is buffered, so four message listeners can be guaranteed All the collected messages can be completely transmitted to the CPU8 without loss.
[0060] Such as figure 2 As shown, the analysis system 11 includes: an acquisition module 17 for reading messages of the power communication link from the FPGA processor 3, a network analysis module 18 for network analysis of the collected messages, and a network analysis module 18 for The application layer of the analyzed message performs protocol analysis by a protocol analysis module 19 and a scheduling management module 20 for scheduling and management between modules.
[0061] The portable power communication protocol tester of this embodiment also includes a memory 21 connected to the CPU 8, and the memory 21 is a solid state disk (solid state disk). The analysis system 11 also includes a recording module 22 for transmitting the messages read by the acquisition module 17 to the memory for storage after analysis by the analysis system, and statistics for statistical analysis of the analysis results of the network analysis module 18 and the protocol analysis module 19 Analysis module 23.
[0062] Such as image 3 with Figure 4 As shown, the FPGA processor 3 mainly contains a chip U1 with the model number ALTERAEP3C25Q240. The chip U1 mirrors the switch port signal message listener 4, network signal message listener 5, serial signal message listener 6 and MODEM carrier signal message listener 7 The data collected by the four message listeners are processed internally and transmitted to CPU8 through the gigabit Ethernet port. The gigabit Ethernet port of chip U1 is the internal A gigabit MAC soft core is formed. The Gigabit MAC soft core is then connected to the Gigabit PHY of chip U6 (model VSC8601) through its RGMII interface (pin 93 to pin 120), realizes Ethernet physical layer conversion on the PHY, and then passes through the first network The isolation transformer T1 and the A port of the first double-connected RJ45 interface J1 (such as Figure 5 Shown) is connected to CPU8 to realize the connection on the physical link.
[0063] Switch port mirroring signal message listener 4 such as Figure 5 As shown, the mirror port (switch communication link 14) of the external switch is connected to the 100MPHY of chip U5 (model KS8721BL) through the B port of the first dual-connected RJ45 socket J1 via the second network isolation transformer T2, and is implemented on chip U5 After the Ethernet physical layer is converted, the received data is transmitted to the FPGA processor 3 through the standard RMII port for processing. FPGA processor 3 implements a 100M MAC on its internal BANK3, and then through the RMII port (63-80 pins of chip U1) and chip U5 (such as Figure 5 Shown) PHY docking.
[0064] Network message listener such as Image 6 As shown, the A and B ports of the second dual-connected RJ45 socket J2 are respectively used as the input and output ports of the external network (network communication link 15) signal. The A and B ports are internally directly connected physically, which can ensure detection When listening, it does not cause damage to the normal communication of the external network. The two signals sent and received from the external network are respectively transmitted to the 100M PHY of two chips U3 and U4 (model KS8721BL) through the third and fourth network isolation transformers T3 and T4, and the Ethernet physical layer is realized on the two chips U3 and U4 After the conversion, it is transmitted to the FPGA processor 3 through the RMII port for processing. FPGA processor 3 implements two 100M MACs on its internal BANK1 and BANK2, and respectively through the RMII port (chip U1 has 4-22 pins and 38-57 pins) and two PHY chips U3 and U4 (such as Image 6 Show) to achieve docking.
[0065] Such as Figure 7 As shown, the serial message listener 6 is a three-in-one serial message listener, which provides three communication interfaces: RS485, RS422 and RS232. Its main function is to realize level conversion and drive between several serial digital interfaces. , And convert the signal received from the serial power communication link 13 into a unified TTL level UART signal and send it to the FPGA processor 3 for processing. When the serial power communication link 13 that needs to be monitored is RS485 communication mode, the A (RX+) and B (RX-) of the RS485 interface of the external serial device are connected to the chip U8, U9, U10 or U14 (model ADM485AR) respectively 6, 7 on the two pins. After the chip U8, U9, U10 or U14 completes the RS485 level to TTL level conversion, the received data is output to the serial data receiving end of the FPGA processor 3 through its pin 1 (the chip U1's 145, 139, 214, On pin 226); In RS485 listening mode, the serial message listener 6 can simultaneously listen to 4 RS485 serial ports. When the serial port power communication link 13 that needs to be monitored is RS422 communication mode, two RS485 ports are used to listen to an external target RS422 link. One RS485 is connected to the Y (TX+) and Z (TX-) lines of the external target RS422 transmission link, and the other RS485 is connected to the A (RX+) and B (RX-) lines of the RS422 receiving link on. When the serial port power communication link 13 that needs to be monitored is the RS232 communication mode, the serial port message listener 6 uses two RS232 receptions to listen to the two sending and receiving lines of an external target RS232 link. The receiving end or sending end of the external target RS232 link is connected to the 16 pins of the chip U11 or U12, U13, U15 (model SP3223EEY), after the chip U11 or U12, U13, U15 completes the RS232 level to TTL level conversion , Output the received data to the serial data receiving end of FPGA processor 3 (on the 144, 142, 216, 230 pins of the chip U1) through its 15 pins.
[0066] MODEM carrier signal message listener 7 such as Figure 8 with Picture 9 As shown, the MODEM carrier signal message listener 7 provides two MODEM carrier receiving interfaces, which can be used to listen to one MODEM communication target link (carrier power communication link 16). The two receiving interfaces of the MODEM carrier signal message listener 7 are respectively connected to a pair of receiving and transmitting lines of the target link. The carrier analog signal is coupled to the modulation and demodulation chip U16, U17 (model MC145503) through the fifth and sixth isolation transformers T5 and BT5 for demodulation, and then is serial-to-parallel converted through the chips U18 and U19 (model 74HC299), and then parallel The data is then sent to the single-chip microcomputers U20 and U21 (model STC89c51Rc) for decoding, and the decoded data is sent to the FPGA processor 3 through the 11 pins of the single-chip microcomputers U20 and U21 in a TTL level serial signal mode for data processing.
[0067] The portable power communication protocol detector of this embodiment adopts FPGA processor 3 to directly realize data recording and buffering at the MAC layer, and exchanges data with CPU8 through a network cable. There are three important bandwidth indicators. One is the total bandwidth of the listening interface. , The second is the writing speed of the hard disk, and the third is the network cable bandwidth. To achieve complete and effective detection, the total bandwidth of the listening interface should be less than the hard disk writing speed, and the network cable bandwidth should be greater than the sum of the total bandwidth of the listening network port and the hard disk writing speed, with margin. The bandwidth index designed by the detector in this embodiment is: the interface bandwidth of each message listener is 100Mbps (during a network storm), then the total interface bandwidth of the four message listeners=4×100Mbps=400Mbps; now generally The write speed of the SSD hard disk is 80MB/s-100MB/s, that is, 640Mbps-800Mbps; the network cable bandwidth is gigabit bandwidth. It can be seen that the designed bandwidth of the detector of this embodiment can meet the requirement of not losing data during detection.
[0068] Obviously, the above-mentioned portable power communication protocol detector of this embodiment can be simplified and changed. The solutions are: 1) Switch port mirroring signal message listener 4, network signal message listener 5, serial signal message listener 6 and MODEM carrier signal message listener 7 The four message listeners can also retain only one, two or three of them, or add message listeners for other communication methods; 2) FPGA processor 3 and the specific circuit structure of the four message listeners are not limited to the circuit structure of this embodiment; 3) The output terminal of the FPGA processor 3 can also be serially connected to the CPU 8 through a PCI bus or other connection methods; 4) memory 21 And the recording module 22 can also be omitted. The detector of this embodiment only performs real-time detection and analysis without recording; 5) The FPGA processor 3 can also be replaced by multiple single-chip microcomputers or other parallel-to-serial processors that work together.
[0069] The detection method of the portable power communication protocol detector of this embodiment, such as Picture 10 As shown, including the following steps:
[0070] 1) Start the tester, configure the parameters of the power communication link to be tested through the input 9 and associate and specify specific protocols to form a system configuration file,
[0071] ----Specific association designation is to select the syntax model file and semantic model file corresponding to the specific protocol of the power communication link to be detected,
[0072] ----The syntax analysis model file and the semantic analysis model file are imported into the detector through the input device 9 by preset or on-site,
[0073] ----The dispatch management module 20 mirrors the switch port according to the system configuration file. Signal message listener 4, network signal message listener 5, serial signal message listener 6 and MODEM carrier signal message listener 7 Set the working parameters of four message listeners and FPGA processor 3;
[0074] 2) The analysis system is initialized, that is, the CPU 8 first loads the dispatch management module 20, the network analysis module 18 and the acquisition module 17, the recording module 22 and the statistical analysis module 23. The dispatch management module 20 then loads the protocol analysis module 19 according to the system configuration file.
[0075] ----The protocol analysis module 19 is a general module that forms the syntax and semantic environment of a specific protocol through the grammar model file and the semantic model file and performs grammatical and semantic analysis on the specific protocol. That is, there is only one protocol analysis module in the analysis system. The statutes are identified by syntax model files and semantic model files,
[0076] ----Loading the network analysis module 18 is to generate the protocol layer, syntax analyzer, session channel manager, and semantic analyzer for the OSI (Open System Interconnection) model, and then organize the protocol layer into a protocol stack, and then Each protocol layer is equipped with a corresponding syntax analyzer and session channel manager, and then a semantic analyzer is configured for each session channel manager
[0077] ----The loading protocol analysis module 19 is initialized according to the syntax model file and semantic model file specified in the system configuration file, that is, the protocol layer, syntax analyzer, session channel manager, semantic analyzer for the specific protocol is generated, and then Organize the protocol layer into a protocol stack, and then equip each protocol layer with a corresponding syntax analyzer and session channel manager, and then configure a semantic analyzer for each session channel manager;
[0078] 3) Switch port mirroring signal message listener 4, network signal message listener 5, serial signal message listener 6 and MODEM carrier signal message listener 7 Four message listeners communicate through power The link listens to the messages of the power communication link. The serial port signal message listener 6 and the MODEM carrier signal message listener 7 (non-Ethernet power communication link message listener) first generate an Ethernet frame Network UDP packets, and then use the intercepted packets as the application layer of the UDP packets. The next four packet listeners will transmit the directly intercepted Ethernet packets to FPGA processor 3 and FPGA processor 3 in parallel. Add a timestamp to the messages received in parallel, and buffer the timestamped messages, and buffer the messages transmitted by the four message listeners;
[0079] 4) The acquisition module 17 reads the buffered message from the FPGA processor 3 and sends the message to the network analysis module 18. The acquisition module 17 sends the message to the recording module 22 after the analysis of the message is completed, and records The module 22 then transmits the message to the memory 21 for storage;
[0080] 5) The network analysis module 18 performs network syntax and semantic analysis on the message sent to the network analysis module to the application layer of the message according to the syntax and semantics of each protocol layer of the 0SI model, and sends the application layer message to the protocol analysis module ,
[0081] ----Network syntax and semantic analysis is to use a syntax analyzer at each protocol layer from the bottom of the protocol stack to perform syntax analysis on the message sent to the network analysis module 18, and pass the obtained syntax analysis tree to The session manager. The session manager distributes the syntax analysis tree to the semantic analyzers at the receiving and sending ends of the session manager for semantic analysis. The syntax analyzer and semantic analyzer respectively send the remaining application layer messages and semantic analysis results to the protocol The upper layer of the stack transfers, and the upper layer performs the above process again until it reaches the application layer of the protocol stack, the top of the protocol stack or the end of the message) to obtain the network analysis result of the message sent to the network analysis module 18,
[0082] ----Send application layer messages to protocol analysis module 19 for protocol analysis, and send network analysis results to statistical analysis module 23 for statistics and display;
[0083] 6) The protocol analysis module 19 analyzes the protocol syntax and semantics of the application layer message according to the syntax and semantics of the protocol,
[0084] ---- Protocol syntax and semantic analysis is to use a syntax analyzer to analyze the application layer messages from the bottom of the protocol stack to the session manager in sequence at each protocol layer, and pass the obtained syntax analysis tree to the session manager. The session manager distributes the syntax analysis tree to the semantic analyzers at the receiving and sending ends of the session manager for semantic analysis. The syntax analyzer and the semantic analyzer respectively send the remaining application layer messages and semantic analysis results to the protocol stack. The upper layer transfers, the upper layer repeats the above process until the top of the protocol stack or the end of the message is reached, the protocol analysis result of the application layer message is obtained, and the protocol analysis result is sent to the statistical analysis module for statistics and display ,
[0085] 7) The network analysis module 18 and the protocol analysis module 19 send their analysis results to the statistical analysis module 23 for statistical analysis, that is, extract the value of part of the message structure in the analysis result and make a chart, after at least two frames of messages The extracted values are calculated and compared to form statistical results, and then the statistical results are sent to the display interface.
