ONO side wall etching process for reducing dark current

Abstract

The invention relates to an ONO side wall etching process for reducing dark current, which comprises the following steps: providing a P-type doped semiconductor substrate comprising a surface area; forming a gate oxide covering the surface area; forming a first gate structure for covering a first part of the gate oxide, wherein the first gate structure is provided with an upper surface area and at least one lateral surface area; forming an N-type impurity area in part of the semiconductor substrate so as to at least form a photodiode device area with the N-type and the P-type doped areas; forming a blanket type side wall layer for covering at least the first gate structure, wherein the side wall structure comprises an oxide layer-nitride layer-oxide layer structure; and using the blanket type side wall layer to form one or more side wall structures of the first gate structure, and simultaneously retaining part of the oxide layer of the oxide layer-nitride layer-oxide layer structure to cover at least the photodiode device area.

Description

technical field [0001] The present invention relates to manufacturing processes of integrated circuits and semiconductor devices, and more particularly, the present invention provides a method and structure for manufacturing a CMOS image sensor that reduces dark current for advanced applications. It should be recognized, however, that the invention has broader applicability. Background technique [0002] Integrated circuits have grown from a handful of interconnected devices fabricated on a single silicon chip to millions of devices. Conventional integrated circuits have performance and complexity far beyond what was originally envisaged. To achieve improvements in complexity and circuit density (i.e., the number of devices that can be packed into a given chip area), the size of the smallest device feature, also known as device "geometry," has also become smaller with each generation of integrated circuits. smaller. [0003] Increasing circuit density not only improves th...

AI Technical Summary

Problems solved by technology

Making devices smaller is very challenging because each process used in the construction of integrated circuits has limitations

That is, a given process can usually only be processed down to a certain feature size, and then a change in process or device layout is required

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