Semiconductor memory device

Abstract

The invention provides a semiconductor memory device which can fully ensure the rising time of the drain voltage of a memory cell in such as EEPROM, has low power consumption and supplies high enoughvoltage to the memory cell. A drain voltage generator circuit (50) includes a first switching element (51) coupled between a first power supply voltage and an output end of the drain voltage generatorcircuit, a second switching element (52) coupled in parallel to the first switching element (51) and having a smaller current capability than that of the first switching element (51), and a control circuit (53) for turning ON the second switching element (52) and then the first switching element (51), and generates a voltage to supply to a drain of a memory cell (11). A source of the memory cell(11) is set to be floated or grounded by a transistor (40).

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory). Background technique [0002] In EEPROM, the storage content of the storage unit can be deleted and rewritten through electrical signals. Specifically, the word line connected to the gate of the memory cell is activated to select the memory cell, a prescribed voltage is applied to the drain of the memory cell according to a control signal for writing data into the memory cell, and the source is changed to a ground state or Floating state. When the source of the memory cell is grounded, thermal electrons are injected into the memory cell, and L data is written as a result. On the other hand, if the source of the memory cell is in a floating state, a tunnel current is generated, and as a result, H data is written. [0003] When the drain voltage of a memory cell is rapidly raised, ...

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Problems solved by technology

However, if the current capability is lowered, a voltage drop occurs, and there is a problem that a sufficient drain voltage cannot be supplied to the drain of the memory cell.

In addition, since the conventional drain voltage generating circuit is configured to discharge the voltage supplied from the gate of the transistor to the ground node except when writing data, there is a problem of large power consumption.

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