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Metal oxide semiconductor structure with stress area

A technology of oxidizing semiconductors and stress regions, applied in semiconductor devices, transistors, electric solid devices, etc., can solve problems such as limited stress effect

Active Publication Date: 2010-02-17
EON SILICON SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the stress layer is too thick, it will affect the difficulty of subsequent caulking
If it is too thin, the stress effect produced will be limited

Method used

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  • Metal oxide semiconductor structure with stress area
  • Metal oxide semiconductor structure with stress area
  • Metal oxide semiconductor structure with stress area

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Experimental program
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Embodiment Construction

[0028] In order to fully understand the purpose, features and effects of the present invention, the present invention will be described in detail through the following specific embodiments in conjunction with the accompanying drawings, which will be described later. In these different drawings and embodiments, the same components will use the same symbols.

[0029] refer to figure 1 , is a cross-sectional view of a wafer according to an embodiment of the present invention. The figure shows that a first component region 112 and a second component region 114 are formed on a semiconductor substrate 100. The first component region and the second component region are N-channel or P-channel or a mixture of both. In this embodiment, it is N channel. On the semiconductor substrate 100, a source 104 (source), a gate 106, a tunneling oxide layer 106a (tunneling oxide layer), a floating gate 106b (floating gate), a dielectric layer 106c, a control gate 106d (control gate), A first ox...

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Abstract

The invention relates to a metal oxide semiconductor structure with a stress area, which comprises a substrate, the stress area, a potential barrier plug and a plurality of oxide layer spacers, wherein the substrate is provided with a first component area and a second component area; the stress area is positioned in the first component area and the second component area comprising a first part anda second part respectively, and the first part and the second part generate different stress; the potential barrier plug separates the first component area and the second component area; and the plurality of oxide layer spacers are positioned between the first part and the potential barrier plug, and are closely adjacent to the first part. Because the stress generated by the stress area increasesthe carrier mobility so as to increase reading current, low reading voltage can be used to reach originally required reading current so as to reduce the possibility of voltage-induced leakage currentto improve the storability of data.

Description

technical field [0001] The present invention relates to a metal-oxide-semiconductor (MOS) structure, and more particularly to a metal-oxide-semiconductor structure with a stress region. Background technique [0002] With the advancement of technology, the process technology of flash memory has also entered the nanometer era. In order to accelerate the operating speed of components, increase the integration of components, and reduce the operating voltage of components, etc., the channel length and oxide layer of the component gate Thickness shrinkage is an inevitable trend. The component gate line width has changed from the previous micron (10 -6 meters) down to the current nanometer (10 -9 Meters), however, with the miniaturization of components, it also brings many problems, such as: the voltage-induced leakage current (stree-induced leakage current, SILC) and the shortening of the gate line width will make the short channel effect (Short Channel Effect) It is getting mo...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L27/12
Inventor 陈宏玮吴怡德
Owner EON SILICON SOLUTION
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