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Circuit for parallel measurement of hot carrier injection effect

An injection effect, hot carrier technology, applied in the direction of circuit, semiconductor/solid-state device testing/measurement, electrical components, etc., can solve the problems of delaying data analysis time, wasting machine testing time, limiting machine capacity, etc., to achieve efficiency high effect

Active Publication Date: 2013-05-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

So it takes 36 hours
This wastes machine testing time, delays data analysis time, and limits machine capacity, thus increasing costs

Method used

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  • Circuit for parallel measurement of hot carrier injection effect
  • Circuit for parallel measurement of hot carrier injection effect
  • Circuit for parallel measurement of hot carrier injection effect

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Experimental program
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Embodiment Construction

[0022] The parallel hot-carrier test circuit of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0023] Hot carrier injection testing usually includes a stress application phase and a device parameter measurement phase. In the stress application stage, a certain stress voltage is applied to the drain and gate of the device under test (DUT, Device Under Test) and after a certain test time, the source and the substrate are grounded. There are three different options for the applied stress: the gate-source voltage is taken when the substrate current is at its maximum value, or when the gate current is at its maximum value, or the gate-source and drain-source voltages are equal. However, these three methods all follow an empirical rule, that is, if the drain-source voltages of different groups of devices are equally different, their gate-source voltages will also be equally different. Such a gate-sourc...

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PUM

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Abstract

The invention provides a circuit for parallel measurement of hot carrier injection effect, which is characterized by comprising a stress voltage applying unit and a DUT unit row consisting of a plurality of DUT(Device Under Test) units, wherein the stress voltage applying unit can apply different stresses to the DUT units. In the circuit, as different stress voltages are applied to the DUT units respectively, the hot carrier tests can be made on a plurality of DUT units in parallel at the same time, and the efficiency is relatively high.

Description

technical field [0001] The invention relates to the field of semiconductor testing, and relates to a method for simultaneously performing hot carrier testing of multiple devices. Background technique [0002] At present, for the VLSI manufacturing industry, with the continuous reduction in the size of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, it has now shrunk to submicron and deep submicron, and is developing towards ultra-deep submicron, but in While the size of the MOS device is proportionally reduced, the operating voltage of the device is not proportionally reduced, which greatly increases the formation probability of channel hot carriers, and generates an interface state at the silicon-silicon dioxide interface, or is blocked by the gate Charge traps in the oxide layer lead to increased degradation of device characteristics such as threshold voltage, transconductance, and leakage current in the linear and saturation regions. [0003] In submi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L21/66G01R31/26
Inventor 高超
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP