Memory system topologies including a buffer device and an integrated circuit memory device

Abstract

Systems, among other embodiments, include topologies (data and / or control / address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control / address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

Description

[0001] related application [0002] This application is a continuation-in-part of U.S. Patent Application Serial No. 11 / 460,899 filed July 28, 2006 (still pending), which was filed September 26, 2005 Continuation in part of Serial No. 11 / 236,401 (still pending). technical field [0003] The present invention relates generally to integrated circuit devices, high speed signal transmission for these devices, memory devices and memory systems. Background technique [0004] Several contemporary trends predict that processors such as general-purpose microprocessors and graphics processors will continue to increase system memory and data bandwidth requirements. Using parallelism in applications such as multi-core processor architectures and multiple graphics pipelines, processors should be able to drive system bandwidth increases at a rate that some predict will double every three years for the next few decades. There are several major trends in dynamic random access memory ("DR...

AI Technical Summary

Problems solved by technology

There are several major trends in Dynamic Random Access Memory ("DRAM") that make DRAM expensive and challenging to keep up with increased data bandwidth and system memory requirements

For example, improvements in transistor speed relative to feature size in a given DRAM technology node and the rising capital investment costs required to advance DRAM technology to higher memory densities for a given DRAM die adversely affect how DRAM technology can keep up Increased data bandwidth and system capacity require speed

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