Speech synthesis device, method and monitor applied thereby
A speech synthesis and speech library technology, applied in speech synthesis, speech analysis, instruments, etc., can solve problems such as affecting the quality of synthesized speech and increasing power consumption, and achieve the effect of avoiding delay and improving quality
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Embodiment 1
[0025] Embodiment 1: as Figure 5 As shown, the data filling mechanism unit 230 in this embodiment is set inside the IC integrated chip. For example, this embodiment uses ADI's ADSP-BF531 high-performance Blackfin processor up to 600MHZ. The ADSP-BF531 processor has a serial port, three counter / timers with PWM (pulse width modulation) and pulse measurement capabilities, a real-time clock, a core timer, an on-chip memory up to 148Kbytes, event controller, etc. and other peripherals. The event controller consists of two parts: the core event controller (CEC) and the system interrupt controller (SIC). The core event controller (CEC) and the system interrupt controller (SIC) work together to control the priority and control all system events . Generally speaking, interrupts from peripherals enter the SIC, and then are directly sent to the general interrupt of CEC for processing. The system interrupt controller SIC provides mapping and routing to the CEC general interrupt input f...
Embodiment 2
[0031] Embodiment 2: as Image 6 As shown, the difference between this embodiment and the above-mentioned Embodiment 1 is: the data loading mechanism unit 230 in this embodiment is composed of two parts: the data loading controller 232 and the peripheral interrupt source 233 as the first priority interrupt source Here, the peripheral interrupt source 233 is set outside the IC integrated chip for implementing speech synthesis, and is composed of an off-chip timer or counter, and the event attribute of the interrupt source is set as a non-maskable interrupt. During the working process of the PWM speech synthesis device in this embodiment, the peripheral interrupt source 233 will send an interrupt request to the processor core 221 through the event controller 222 at regular intervals, and send a control signal to the data filling controller 232 . The PWM speech synthesis device of this embodiment can also be implemented by using ADI's ADSP-BF531 high-performance Blackfin processo...
Embodiment 3
[0032] Implement 3: on the basis of embodiment 1 or 2, such as image 3 As shown, the PWM converter 240 of the present embodiment includes: a counter and a comparator; the counter counts according to a certain cycle cycle, and regularly inputs digital voice data at one input end of the comparator, and at the other input end of the comparator The value of the input counter is compared with the two, and the output pulse width modulation pulse is used to drive the operational amplifier and power amplifier circuit, and the voice can be reproduced. The other components and connections of this embodiment are the same as those of Embodiment 1 or 2. If the ADSP-BF531 is also used in this embodiment, the PWM converter 240 can be realized by three timers built on and off the chip.
[0033] Based on the above scheme, the present invention also provides a monitor, which includes Figure 4 The speech synthesis device, which contains: a follow-up circuit for connecting the output end of t...
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