Rate adaption method and device
A technology of rate matching and starting position, applied in the field of communication, can solve the problem of high probability of rate matching processing overlapping phenomenon, and achieve the effect of avoiding overlapping phenomenon and enhancing performance
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example 1
[0100] Example 1, the present invention will be described in detail below by taking 1 / 3 code rate as an example (but not limited to 1 / 3 code rate).
[0101] Such as Figure 11 Shown, under the situation of 1 / 3 code rate, the processing procedure of the present invention is as follows:
[0102] (111) The information that length is K is sent to 1 / 3 code rate Turbo code encoder, produces a system bit stream S and the first, the second parity bit stream P1 and P2;
[0103] (112) For the code word compiled by the Turbo encoder, the system bit stream S and the first and second parity bit streams P1 and P2 are respectively interleaved in a block through a sub-interleaver to generate a new system bit stream S and the first bit stream 1. The second verification bit streams P1 and P2;
[0104] (113) Put the system bits in front of the circular buffer, and the first and second parity bit streams are interleaved and placed behind the system bit streams through an inter-block interleaver...
example 2
[0128] In Example 2, the present invention will be described in detail below by taking 1 / 3 code rate as an example (but not limited to 1 / 3 code rate).
[0129] Such as Figure 12 Shown, under the situation of 1 / 3 code rate, the processing procedure of the present invention is as follows:
[0130] (121) The information that length is K is sent to 1 / 3 code rate Turbo code encoder, produces a system bit stream S and the first, the second parity bit stream P1 and P2;
[0131] (122) the code word compiled by the Turbo encoder, the system bit stream S and the first and second check bit streams P1 and P2 are stored in the memory;
[0132] (123) For the codeword in the memory, the system bit stream S and the first and second parity bit streams P1 and P2 are respectively interleaved in the block through the address generator to generate a new system bit stream S and the first and second check bit streams Verify bit streams P1 and P2 to form a virtual circular buffer;
[0133] (124) ...
Embodiment 1
[0160] In the first embodiment, a rate matching device is provided.
[0161] Such as Figure 15 As shown, the rate matching device according to Embodiment 1 includes:
[0162] Encoder (also can be referred to as mother code encoder) 10, is used for encoding information grouping, produces the code word that length is L;
[0163] An interleaving module (also referred to as an interleaver) 20, configured to interleave a codeword sequence of length L;
[0164] Circular buffer (not shown), for storing the interleaved mother code word sequence of length L;
[0165] The rate matcher (also referred to as a sub-packet generating device) 30 is configured to select codeword bits from the mother code codeword to generate a currently transmitted HARQ sub-packet. Further includes:
[0166] In the case of the first transmission of a HARQ subpacket, select the first L from the mother code word of length L 1 bits constitute the HARQ subpacket for the first transmission, where L 1 is the ...
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