Method of layout design of laterally diffused MOS transistor

Abstract

The invention discloses a method of a layout design of a laterally diffused MOS transistor, which adopts the grid-shaped layout design and designs wells of a source region and a drain region of the laterally diffused MOS transistor in square shape, each well as the source region is surrounded by the well as the drain region, and each well as the drain region is surrounded by the well as the source region at the same time, then a square region with a smaller side length is defined as an active region of the drain region in the square of the well as the drain region, the well as the source region and a thin oxide layer defining region of the drain region are acted as an active region, and the rest annular part of the well as the drain region is acted as a field oxide region, polycrystalline silicon is arranged at the connecting part of the square of the source region and the square of the drain region and covers whole channel region and partial field oxide region, and a buried layer ion implantation region is added below a silicon epitaxial layer of the whole region. The method of the layout design can realize the optimization of the array area.

Description

technical field [0001] The invention relates to a layout design method of a lateral diffusion transistor. Background technique [0002] The layout design of semiconductor devices is a necessary process before chip preparation, which is used to reasonably distribute the various parts of multiple identical transistors on the silicon substrate according to the designed circuit. In layout design, the minimization of chip device area is the ultimate goal of designers. Laterally diffused MOS transistor (LDMOS) is a kind of MOS transistor, figure 1 It is a cross-sectional view of an N-type laterally diffused MOS transistor formed on an N-type epitaxial layer (NEPI). The channel region and source region of the device are in the low-voltage P-well region (LVPW), and the drain region (Drain) is a high-voltage N-well region. (HVNW). Between the field oxide layer (Field) is the active region (Active), which is divided into N-type region (N+) and P-type region (P+), among which the N+...

AI Technical Summary

Problems solved by technology

The current direction of the transistor array designed with this structure is fixed, generally only the current along the cross-sectional direction, and the optimization of the array area cannot be realized

Due to the large drain area of ​​conventional LDMOS, the junction depth also includes the drift region, so the drain resistance is large, and it is difficult to improve its resistance through technological means

At the same time, the arrangement of LDMOS transistors with an interdigitated structure cannot achieve uniform wiring.

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