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Forming method of lateral wall substrate and forming method of lateral wall

A sidewall and base layer technology, applied in electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as uneven junction depth control, uneven thickness distribution of oxide layers, and influence on device electrical performance, and achieve enhancement and reduction. , Reduce the thickness difference and enhance the effect of surface flatness

Inactive Publication Date: 2012-06-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Claims
  • Application Information

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Problems solved by technology

[0007] However, it has been found in actual production that after the formation of the sidewall base layer / sidewall, the thickness distribution of the oxide layer remaining on the substrate is extremely uneven, that is, it is located in the central region of the substrate (taking the 300mm process as an example, with a radius of There is a large thickness difference between the oxide layer of the area covered by 0 to 50mm) and the edge area (taking the 300mm process as an example, the area covered by the radius of 50mm to 150mm), specifically, as Figure 5 As shown, in practice, after the sidewall is formed, the thickness difference between the oxide layer located in the central region of the substrate and the edge region can be as high as 62.26-47.5415=14.7185 angstroms; since the remaining oxide layer will be formed later As a protective layer in the process of the ultra-shallow junction, it is beneficial to control the junction depth of the ultra-shallow junction, and its uneven thickness will lead to uneven control of the junction depth, and thus affect the electrical performance of the device

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  • Forming method of lateral wall substrate and forming method of lateral wall
  • Forming method of lateral wall substrate and forming method of lateral wall
  • Forming method of lateral wall substrate and forming method of lateral wall

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[0051] As a first embodiment of the present invention, the bias parameter is set to zero in the early stage of the process of etching the second dielectric layer. That is, the step of etching the second dielectric layer includes: Figure 9 As shown, the etch front with a bias parameter of zero; and, as Figure 10 As shown, the post-etch segment where the bias parameter is not zero.

[0052] In the front stage of the etching, the selected process condition is CF 4 The flow rate is 30sccm; CHF 3 The flow of Ar is 90sccm; the flow of Ar is 180sccm; O 2 The flow rate is 20sccm; the reaction voltage is 150V; the reaction pressure is 35mTorr; the magnetic induction is 0.

[0053] In the back stage of the etching, the selected process condition is CF 4 The flow rate is 30sccm; CHF 3 The flow of Ar is 90sccm; the flow of Ar is 180sccm; O 2 The flow rate is 20sccm; the response voltage is 150V; the response pressure is 35mTorr; the magnetic induction intensity can be 5G. Or, wh...

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Abstract

The invention relates to a forming method of a lateral wall substrate, which comprises the following steps of: forming a grid electrode on a base; forming a first dielectric layer on the surface of the base on which the grid electrode is formed and covering the first dielectric layer on the grid electrode; forming a second dielectric layer on the first dielectric layer; and etching the second dielectric layer by using the first dielectric layer as a stop layer to form the lateral wall substrate surrounding the grid electrode, wherein at least at the previous period of the process of etching the second dielectric layer, an offset parameter is set as zero, thereby reducing the thickness difference between the first dielectric layer reserved at the central area of the base and the first dielectric layer reserved at the marginal area. The invention also provides a forming method of a lateral wall and can reduce the thickness difference between a silicon oxide layer reserved at the centralarea of the base and the silicon oxide layer reserved at the marginal area.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a base layer of a sidewall and a method for forming a sidewall. Background technique [0002] In the semiconductor manufacturing process, spacers are used to surround the gate to prevent source-drain (S / D) implantation of a larger dose from being too close to the channel to cause source-drain punchthrough. [0003] As the critical dimension of the device decreases, the short channel effect becomes more and more obvious. In order to reduce the occurrence of the short channel effect, after forming the gate on the substrate, before performing lightly doped ion implantation, it also includes forming a sidewall base layer (offset spacer) step; so that when lightly doped ion implantation is performed, the gate and the sidewall base layer can be used as an ion implantation mask, that is, the operation of forming the sidewall base layer will affec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/311H01L21/336
Inventor 赵林林韩宝东
Owner SEMICON MFG INT (SHANGHAI) CORP
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